How to explain the summation of bus signal to a reg?

[Robert Willy]

Hi,

When I write the following code, I incorrectly forget to add [7:0] before yY.
When the code is simulated,
prod1='01010100';
prod2='11110100';
prod3='11111110';

yY ='00000000';

I cannot figure out what logic behind it making yY ='00000000';

Could you tell me?



.................
reg [7:0] X1, X2;
reg yY;
reg [7:0] prod1, prod2, prod3;

always @ (posedge clk) begin
if(validsample) begin
X1 <= X;
X2 <= X1;
prod1 <= A * X;
prod2 <= B * X1;
prod3 <= C * X2;
end

yY <= prod1 + prod2 + prod3;
end

 

[Sharad]

yY is declared as a single bit reg. I am curious how the simulation showed '00000000' instead of just a single bit value. Are you seeing the reported value of yY after validsample signal is true or before it becomes true? Which tool is the simulator?

 

[Robert Willy]

On Friday, August 14, 2015 at 10:55:50 PM UTC-7, Sharad wrote:
> yY is declared as a single bit reg. I am curious how the simulation showed '00000000' instead of just a single bit value. Are you seeing the reported value of yY after validsample signal is true or before it becomes true? Which tool is the simulator?

Sorry, I may give the Y value ([7:0]) to yY.
I figure it out the yY is the LSB of the summation of 3 prod? above.
Thanks,

 

[dsc]

Since yY is only one bit, only bit zero of the sum of prods will be assigned to yY. You may see if you vary the prod values, it change to one.