how to do a 1 to 4 demultiplexer in vhdl?

[MNQ]

Hi All

I'm trying to figure out how I can write a 1 to 4 demultiplexer in VHDL.
The demux will output one 8 bit serial data on each output, as its selected.
Two of the outputs need to keep the last value ie stay high or stay low. I
have thought of using the CASE construct. Would this be the way to go and
does it have to be used within a PROCESS? Its also got to stop cycling once
all 4 outputs have been used and then wait until more data is sent. Then go
through the process again. But I think I have this bit covered.

Can anyone help with the 1 to 4 demux stage?

Thanks

MNQ

 

[Pieter Hulshoff]

I have thought of using the CASE construct. Would this be the way to go
and does it have to be used within a PROCESS?

A CASE statement within a process sounds like a clean way to me. You could
also use concurrent assignment statements with the WHEN clause.

Regards,

Pieter Hulshoff