How to Divide a clock by 2

Guest
Im trying to learn an HDL, and just trying to do a simple clock divide,
but not sure when to use 'reg' or when to use 'wire'. The xilinx ise
8.1 synthesizer complains about dclk below:


module test(clk);
input clk;

reg [1:0] CounterZ;
reg dclk; //input clk divided by 2
wire dclk;

always @(posedge clk)
CounterZ <= CounterZ + 1;

dclk = CounterZ(0);
 
Procedural statements must be acted on by variables defined as 'reg'. In
your case you have dclk getting assigned with a procedural statement and
defined as both wire and reg.

Define dclk as reg only and put begin and end around the last two
statements. Also change the dclk assignment to a non-blocking assignment by
using the syntax <= instead of just =.

You also need an output defined for the module, see below.

module divide_by_two (clk, dclk);

input clk;
output reg dclk;

reg [1:0] CounterZ;

always @(posedge clk)
begin
CounterZ <= CounterZ + 1;
dclk <= CounterZ[0];
end
endmodule


<benn686@hotmail.com> wrote in message
news:1139877350.632941.308300@z14g2000cwz.googlegroups.com...
Im trying to learn an HDL, and just trying to do a simple clock divide,
but not sure when to use 'reg' or when to use 'wire'. The xilinx ise
8.1 synthesizer complains about dclk below:


module test(clk);
input clk;

reg [1:0] CounterZ;
reg dclk; //input clk divided by 2
wire dclk;

always @(posedge clk)
CounterZ <= CounterZ + 1;

dclk = CounterZ(0);
Click to expand...
 
Classic divider:
module divide_by_two (clk, rst, dclk);

input clk, rst;
output reg dclk;

always @(posedge clk or posedge rst)
begin
if(rst) dclk <= 1'b0;
else dclk <= ~dclk;
end
endmodule
 
If you want a clock divider in the Xilinx ISE tool, please use the
built in ones for your FPGA. It is in the manual, and they have very
sophisticated clock dividers that can divide down to any reasonable
range.

When I took the FPGA class, it was an automatic F if you tried to build
your own clock divider. You don't have to write your own.

If this is just a toy project and you want to see what the verilog
looks like michaelst's answer is the best given so far.

-Art
 
Of course there are better ways to implement the divider; I was just trying
to build off of what he already started.


"Art Stamness" <artstamness@gmail.com> wrote in message
news:1140050898.481622.67830@o13g2000cwo.googlegroups.com...
If you want a clock divider in the Xilinx ISE tool, please use the
built in ones for your FPGA. It is in the manual, and they have very
sophisticated clock dividers that can divide down to any reasonable
range.

When I took the FPGA class, it was an automatic F if you tried to build
your own clock divider. You don't have to write your own.

If this is just a toy project and you want to see what the verilog
looks like michaelst's answer is the best given so far.

-Art
Click to expand...
 
Thanks Rob!

Actually your answer was very helpful, not just in how to do the clock
divide, but also in helping me with my confusion of reg vs wire.

So if I understand correctly, a variable should be declared a reg if
its value is dependent on a condition (i.e. 'always @...'), and it
should be declared a wire otherwise? Also, if the signal is to drive
a pin or a signal in another module, then it should also be declared a
reg, correct?

TIA!


Rob wrote:
Of course there are better ways to implement the divider; I was just trying
to build off of what he already started.


"Art Stamness" <artstamness@gmail.com> wrote in message
news:1140050898.481622.67830@o13g2000cwo.googlegroups.com...
If you want a clock divider in the Xilinx ISE tool, please use the
built in ones for your FPGA. It is in the manual, and they have very
sophisticated clock dividers that can divide down to any reasonable
range.

When I took the FPGA class, it was an automatic F if you tried to build
your own clock divider. You don't have to write your own.

If this is just a toy project and you want to see what the verilog
looks like michaelst's answer is the best given so far.

-Art
Click to expand...
 
The above statements are not accurate. You should try getting a good
verilog book, most of this would be layed out better there.

Corrections :

1. A reg or a wire can drive an "output".
2. Wires are assigned using continuous assignments ( done outside of
event triggered blocks : always, initial . . ) . They look like this :

....
wire foo ;
assign foo = a & b ;
....

The expression "a&b" is evaluated whenever a or b change, and the value
of foo is updated with that result. This continuous assignment is used
to model combinational logic, and, or, xor . . . etc.

4. Regs are different. They are procedurally assigned during event
control. So they can exhibit the same behavior as a wire like :

reg foo ;
always @(a or b)
begin
foo = a & b ;
end

The value of foo is caculated when either a or b are changed. The above
code, matches exactly the behavior of the wire above. This is the case
where reg is used to model combinational logic.

But Regs can also be used to model sequential logic, like Flip Flops,
latches, memories :

always @(posedge clk)
begin
foo <= a & b ;
end

This is the modeling of a basic Positive Edge Triggered flip flop. Only
when the positive edge changes is the expression a & b calculated. If a
& b change at any time after that, the value of foo will not be updated
until the next positive edge of the clock, when the expression is
evaluated again.

So when you are talking about modeling a Clock divider, you need to
have a flop, and you need to model it as a reg, whose values change on
the edge of another clock.

I hope this helps.

-Art
 
"Art Stamness" <artstamness@gmail.com> wrote in message
news:1140115347.622929.89570@g47g2000cwa.googlegroups.com...
The above statements are not accurate. You should try getting a good
verilog book, most of this would be layed out better there.
Click to expand...
I have a good book!

Corrections :

1. A reg or a wire can drive an "output".
Click to expand...
Did I say it couldn't?!

2. Wires are assigned using continuous assignments ( done outside of
event triggered blocks : always, initial . . ) . They look like this :
Click to expand...
I'm very familiar on how to drive wires. I don't think I mentioned how to
drive a wire in my response.

...
wire foo ;
assign foo = a & b ;
...

The expression "a&b" is evaluated whenever a or b change, and the value
of foo is updated with that result. This continuous assignment is used
to model combinational logic, and, or, xor . . . etc.

4. Regs are different. They are procedurally assigned during event
control. So they can exhibit the same behavior as a wire like :

reg foo ;
always @(a or b)
begin
foo = a & b ;
end

The value of foo is caculated when either a or b are changed. The above
code, matches exactly the behavior of the wire above. This is the case
where reg is used to model combinational logic.

But Regs can also be used to model sequential logic, like Flip Flops,
latches, memories :

always @(posedge clk)
begin
foo <= a & b ;
end

This is the modeling of a basic Positive Edge Triggered flip flop. Only
when the positive edge changes is the expression a & b calculated. If a
& b change at any time after that, the value of foo will not be updated
until the next positive edge of the clock, when the expression is
evaluated again.

So when you are talking about modeling a Clock divider, you need to
have a flop, and you need to model it as a reg, whose values change on
the edge of another clock.

I hope this helps.

-Art
Click to expand...
 
Rob,

My post was in response to benn's statement :

So if I understand correctly, a variable should be declared a reg if
its value is dependent on a condition (i.e. 'always @...'), and it
should be declared a wire otherwise? Also, if the signal is to drive
a pin or a signal in another module, then it should also be declared a
reg, correct?
Click to expand...
For some reason, when I use the "reply" tab on groups.google.com, it
seems to attach the reply to the last, not to the one I clicked on.

-Art
 
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