Guest
Hi,
Does anyone know how to disable the automatic insertion of "_i" on
signals that are connect to a instance port map?
For example, when I use the vhdl-paste-port-instance command on a
model with the ports called "rst_l" and "clk", it gives me this:
instance: clk_model
port map (
rst_l => rst_l_i,
clk => clk_i);
I want to get rid of the "_i" convention and use identical names for
the port and the signal.
Thanks in advance...
Chris
Does anyone know how to disable the automatic insertion of "_i" on
signals that are connect to a instance port map?
For example, when I use the vhdl-paste-port-instance command on a
model with the ports called "rst_l" and "clk", it gives me this:
instance: clk_model
port map (
rst_l => rst_l_i,
clk => clk_i);
I want to get rid of the "_i" convention and use identical names for
the port and the signal.
Thanks in advance...
Chris