N
navinm
Guest
Hi,
How to determine the exact minimum clock period of a particular design
using Xilinx ise (6.2i) tool, or other tools if possible?
After Placement & route (PAR) Simulation results should come inside that
Minimum clock period (MCP)?
I m asking this question because, xilinx ise (6.2i) is giving me 12.766 ns
of min. clock period in PAR report and i m getting my proper output after
PAR, if i m keeping MCP of design 20 ns? so it is required by me to
investigate proper mechanism to find out the MCP of any design?????
Pls Help me out.
pls reply asap.
How to determine the exact minimum clock period of a particular design
using Xilinx ise (6.2i) tool, or other tools if possible?
After Placement & route (PAR) Simulation results should come inside that
Minimum clock period (MCP)?
I m asking this question because, xilinx ise (6.2i) is giving me 12.766 ns
of min. clock period in PAR report and i m getting my proper output after
PAR, if i m keeping MCP of design 20 ns? so it is required by me to
investigate proper mechanism to find out the MCP of any design?????
Pls Help me out.
pls reply asap.