How to detect the posedge of two clocks (asynchronous to eac

U

Ujjwal Konar

Guest
Hi:

I would like to detect the posedge of two clocks (asynchronous to each other) at the same time. I didn't find any verilog construct to achieve that.

Suppose if two clocks are "clk1" and clk2" respectively, I can't write the construct "always @(posedge clk1 and posedge clk2)" but "and" is not allowed.

Could you please let me know how I can achieve this by means of verilog constructs?

Thanks in advacne. Regards,
Ujjwal.
 
In article <ed159db5-b2f0-4241-a8f4-b0ddee486054@googlegroups.com>,
Ujjwal Konar <ujjwal.konar@gmail.com> wrote:
I would like to detect the posedge of two clocks (asynchronous to each other)
at the same time. I didn't find any verilog construct to achieve that.

Suppose if two clocks are "clk1" and clk2" respectively, I can't write
the construct "always @(posedge clk1 and posedge clk2)" but "and" is
not allowed.
Click to expand...
Verilog will allow this just fine. It can even be more complex than that.
It'll simulate pretty much how you intend.

For synthesis, however, you're out of luck. What hardware exactly would
you want to target?

There's a few special cases - like DDR IO cells. But for all cases that
I'm aware of, synthesis tools are unable to infer this type of logic; you must
instanciate it.

Regards,

Mark
 
In article <k9o4pv$ngp$1@dont-email.me>, Mark Curry <gtwrek@sonic.net> wrote:
In article <ed159db5-b2f0-4241-a8f4-b0ddee486054@googlegroups.com>,
Ujjwal Konar <ujjwal.konar@gmail.com> wrote:

I would like to detect the posedge of two clocks (asynchronous to each
other) at the same time. I didn't find any verilog construct to
achieve that.

Suppose if two clocks are "clk1" and clk2" respectively, I can't write
the construct "always @(posedge clk1 and posedge clk2)" but "and" is
not allowed.

Verilog will allow this just fine. It can even be more complex than that.
It'll simulate pretty much how you intend.
Click to expand...
Actually, I take this back. You issues is the "and". "or" would work
just fine.

You're asking for "and" as in the two clocks' rising edges are exactly
simultaneous? Even in the simulation event queue, there's no "exactly"
simultaneous. You could change it to "or" and then save some variables
with the simtime, and compare.

You trying to model a PLL or something?

--Mark
 
On Thursday, 6 December 2012 00:24:11 UTC+5:30, Mark Curry wrote:
In article <k9o4pv$ngp$1@dont-email.me>, Mark Curry <gtwrek@sonic.net> wrote:

In article <ed159db5-b2f0-4241-a8f4-b0ddee486054@googlegroups.com>,

Ujjwal Konar <ujjwal.konar@gmail.com> wrote:



I would like to detect the posedge of two clocks (asynchronous to each

other) at the same time. I didn't find any verilog construct to

achieve that.



Suppose if two clocks are "clk1" and clk2" respectively, I can't write

the construct "always @(posedge clk1 and posedge clk2)" but "and" is

not allowed.



Verilog will allow this just fine. It can even be more complex than that.

It'll simulate pretty much how you intend.



Actually, I take this back. You issues is the "and". "or" would work

just fine.



You're asking for "and" as in the two clocks' rising edges are exactly

simultaneous? Even in the simulation event queue, there's no "exactly"

simultaneous. You could change it to "or" and then save some variables

with the simtime, and compare.



You trying to model a PLL or something?



--Mark
Click to expand...
Hi Mark:

It is always possible to achieve the purpose here by means of controlling some variable values. I was wondering why verilog language construct does not allow to meet the same objective by means of "and". I know there's no "exactly" simultaneous as long as simulation is concerned, but as we are able to achieve the same purpose by means of taking different route, why language does not allow it simply in a straight forward manner?

Regards,
Ujjwal.
 
In article <0ff4ecf4-4cb9-4f0a-ad98-b30d22434916@googlegroups.com>,
Ujjwal Konar <ujjwal.konar@gmail.com> wrote:
On Thursday, 6 December 2012 00:24:11 UTC+5:30, Mark Curry wrote:
In article <k9o4pv$ngp$1@dont-email.me>, Mark Curry <gtwrek@sonic.net> wrote:

In article <ed159db5-b2f0-4241-a8f4-b0ddee486054@googlegroups.com>,

Ujjwal Konar <ujjwal.konar@gmail.com> wrote:



I would like to detect the posedge of two clocks (asynchronous to each

other) at the same time. I didn't find any verilog construct to

achieve that.



Suppose if two clocks are "clk1" and clk2" respectively, I can't write

the construct "always @(posedge clk1 and posedge clk2)" but "and" is

not allowed.



Verilog will allow this just fine. It can even be more complex than that.

It'll simulate pretty much how you intend.



Actually, I take this back. You issues is the "and". "or" would work

just fine.



You're asking for "and" as in the two clocks' rising edges are exactly

simultaneous? Even in the simulation event queue, there's no "exactly"

simultaneous. You could change it to "or" and then save some variables

with the simtime, and compare.



You trying to model a PLL or something?



--Mark

Hi Mark:

It is always possible to achieve the purpose here by means of controlling some
variable values. I was wondering why verilog language construct does not allow
to meet the same objective by means of "and". I know there's no "exactly"
simultaneous as long as simulation is concerned, but as we are able to
achieve the same purpose by means of taking different route, why language
does not allow it simply in a straight forward manner?
Click to expand...
It's simply not the way the language works. As I said, there's
no simultaneous. That block will execute twice - once for each
positive edge. The "simtime" may be the same for each iteration,
but it's stepping through the code twice.

Read up on the Verilog "Stratified Event Queue". What
you're asking for just doesn't fit inside that framework.

--Mark
 
On Thursday, December 6, 2012 10:16:42 PM UTC+5:30, Mark Curry wrote:
In article <0ff4ecf4-4cb9-4f0a-ad98-b30d22434916@googlegroups.com>,

Ujjwal Konar <ujjwal.konar@gmail.com> wrote:

On Thursday, 6 December 2012 00:24:11 UTC+5:30, Mark Curry wrote:

In article <k9o4pv$ngp$1@dont-email.me>, Mark Curry <gtwrek@sonic.net> wrote:



In article <ed159db5-b2f0-4241-a8f4-b0ddee486054@googlegroups.com>,



Ujjwal Konar <ujjwal.konar@gmail.com> wrote:







I would like to detect the posedge of two clocks (asynchronous to each



other) at the same time. I didn't find any verilog construct to



achieve that.







Suppose if two clocks are "clk1" and clk2" respectively, I can't write



the construct "always @(posedge clk1 and posedge clk2)" but "and" is



not allowed.







Verilog will allow this just fine. It can even be more complex than that.



It'll simulate pretty much how you intend.







Actually, I take this back. You issues is the "and". "or" would work



just fine.







You're asking for "and" as in the two clocks' rising edges are exactly



simultaneous? Even in the simulation event queue, there's no "exactly"



simultaneous. You could change it to "or" and then save some variables



with the simtime, and compare.







You trying to model a PLL or something?







--Mark



Hi Mark:



It is always possible to achieve the purpose here by means of controlling some

variable values. I was wondering why verilog language construct does not allow

to meet the same objective by means of "and". I know there's no "exactly"

simultaneous as long as simulation is concerned, but as we are able to

achieve the same purpose by means of taking different route, why language

does not allow it simply in a straight forward manner?



It's simply not the way the language works. As I said, there's

no simultaneous. That block will execute twice - once for each

positive edge. The "simtime" may be the same for each iteration,

but it's stepping through the code twice.



Read up on the Verilog "Stratified Event Queue". What

you're asking for just doesn't fit inside that framework.



--Mark
Click to expand...
Thanks Mark. After going through the "Stratified Event Queue", I understand that the Verilog event queue is logically segmented into five different regions.
 
On Thursday, December 6, 2012 10:16:42 PM UTC+5:30, Mark Curry wrote:
In article <0ff4ecf4-4cb9-4f0a-ad98-b30d22434916@googlegroups.com>, Ujjwal Konar <ujjwal.konar@gmail.com> wrote: >On Thursday, 6 December 2012 00:24:11 UTC+5:30, Mark Curry wrote: >> In article <k9o4pv$ngp$1@dont-email.me>, Mark Curry <gtwrek@sonic.net> wrote: >> >> >In article <ed159db5-b2f0-4241-a8f4-b0ddee486054@googlegroups.com>, >> >> >Ujjwal Konar <ujjwal.konar@gmail.com> wrote: >> >> >> >> >> >>I would like to detect the posedge of two clocks (asynchronous to each >> >> >>other) at the same time. I didn't find any verilog construct to >> >> >>achieve that. >> >> >> >> >> >>Suppose if two clocks are "clk1" and clk2" respectively, I can't write >> >> >>the construct "always @(posedge clk1 and posedge clk2)" but "and" is >> >> >>not allowed. >> >> > >> >> >Verilog will allow this just fine. It can even be more complex than that. >> >> >It'll simulate pretty much how you intend. >> >> >> >> Actually, I take this back. You issues is the "and". "or" would work >> >> just fine. >> >> >> >> You're asking for "and" as in the two clocks' rising edges are exactly >> >> simultaneous? Even in the simulation event queue, there's no "exactly" >> >> simultaneous. You could change it to "or" and then save some variables >> >> with the simtime, and compare. >> >> >> >> You trying to model a PLL or something? >> >> >> >> --Mark > >Hi Mark: > >It is always possible to achieve the purpose here by means of controlling some >variable values. I was wondering why verilog language construct does not allow >to meet the same objective by means of "and". I know there's no "exactly" >simultaneous as long as simulation is concerned, but as we are able to >achieve the same purpose by means of taking different route, why language >does not allow it simply in a straight forward manner? It's simply not the way the language works. As I said, there's no simultaneous. That block will execute twice - once for each positive edge. The "simtime" may be the same for each iteration, but it's stepping through the code twice. Read up on the Verilog "Stratified Event Queue". What you're asking for just doesn't fit inside that framework. --Mark
Click to expand...


Hii,
I am trying to design some circuit which starts working when two clocks have their rising edges matching. I have tried many things but all in vain.Can u help me how to detect the posedges of two asynchronous clocks at the same time.

thanks in advance.
Giridhar.
 
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