How to detect a combinational feedback loop

[dmitriym]

Hello, experts!


Can somebody advice me how to detect _combinational feedback loops_ in
the design? Is there any tool that can catch path through which such
feedback is propagated? Maybe, some synthesizer can highlight such
loop on the generated schematic drawing?


Thanks in advance!
-dmitriym

 

[Alex]

On Apr 28, 11:54 am, dmitriym <explo...@inbox.ru> wrote:

Hello, experts!

Can somebody advice me how to detect _combinational feedback loops_ in
the design? Is there any tool that can catch path through which such
feedback is propagated? Maybe, some synthesizer can highlight such
loop on the generated schematic drawing?

Thanks in advance!
-dmitriym

Synopsys Design Compiler does it with report_loops" command on already
synthesised designs.
Probably, other synthesis tools can do the same.

Also, most of LINT tools (such as Synopsys LEAD) can find loops in
RTL much quicker.

And finally, simulators such as Modelsim report about combinational
loops (oscilations) during 0-delay gatelevel simulation.

-Alex

 

[dmitriym]

On 28 ÁĐŇ, 23:22, Alex <agnu...@gmail.com> wrote:

On Apr 28, 11:54 am, dmitriym <explo...@inbox.ru> wrote:

Hello, experts!

Can somebody advice me how to detect _combinational feedback loops_ in
the design? Is there any tool that can catch path through which such
feedback is propagated? Maybe, some synthesizer can highlight such
loop on the generated schematic drawing?

Thanks in advance!
-dmitriym

Synopsys Design Compiler does it with report_loops" command on already
synthesised designs.
Probably, other synthesis tools can do the same.

Also, most of LINT tools (such as Synopsys LEAD) can find loops in
RTL much quicker.

And finally, simulators such as Modelsim report about combinational
loops (oscilations) during 0-delay gatelevel simulation.

-Alex

Hello, Alex!

Thanks a lot for your reply!
You've really helped me: I'll try the "reply_loops" command for the
Design Compiler! I guess, it should help.

PS: I've tried the LEDA - it reports only "loop is detected" (it
doesn't report any propagation path). Maybe I've an old version of
this tool...

Regards,
dmitriym

 

[karthik]

Synopsys VCS can also help you in this requirement.

[1] You can try to compile the test case using +vcs+loopreport compile
time switch. Then run the simv using +vcs+loopreport. You may see loop
report.

[2] Please use the option +vcs+loopdetect along with your compilation
command.

%> vcs +vcs+loopdetect ...[other_options]

This directly gives you the loop info.

--Karthik

 

[Tummala Srinivasulu]

On Sunday, 29 April 2007 12:03:42 UTC+1, karthik wrote:

Synopsys VCS can also help you in this requirement.

[1] You can try to compile the test case using +vcs+loopreport compile
time switch. Then run the simv using +vcs+loopreport. You may see loop
report.

[2] Please use the option +vcs+loopdetect along with your compilation
command.

%> vcs +vcs+loopdetect ...[other_options]
This directly gives you the loop info.

--Karthik

Could you please tell me similar one in irun (Cadence incisiv simulator)?

 

On Saturday, April 28, 2007 at 11:54:17 AM UTC-4, dm wrote:

Hello, experts!


Can somebody advice me how to detect _combinational feedback loops_ in
the design? Is there any tool that can catch path through which such
feedback is propagated? Maybe, some synthesizer can highlight such
loop on the generated schematic drawing?

I don't recall the details, but I've never had to do anything special to get loop reports. I'm thinking they come from the timing analyzer since it can't analyze a combinatorial loop for timing. So likely any timing analyzer will give you combinatorial loop reports. You might have to ask it to tell you about logic that is not being analyzed.

Rick C.

 

[vijay.gampa@gmail.com]

On Saturday, 28 April 2007 08:54:17 UTC-7, dm wrote:

Hello, experts!


Can somebody advice me how to detect _combinational feedback loops_ in
the design? Is there any tool that can catch path through which such
feedback is propagated? Maybe, some synthesizer can highlight such
loop on the generated schematic drawing?


Thanks in advance!
-dmitriym

For vcs,
Use loop_detect (https://solvnet.synopsys.com/retrieve/023547.html?otSearchResultSrc=advSearch&otSearchResultNumber=1&otPageNum=1) and
for cadence go through https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nTGDEA2&pageName=ArticleContent&sq=005d0000003U3KuAAK_201714185451450

-Vijay Gampa