How to design this circuit?

[Tobias Weingartner]

I'm looking for some way to figure out a circuit that will lock onto
a signal (0-5v, binary) in such a way that no matter what the current
frequency of the input signal (ok, within reason, 720 p/s to 21600 p/s),
the output signal would be 100 times the input frequency.

In other words, I'd like to have 50 equally spaced pulses occur between
consecutive transitions of the input signal?

--
[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

 

[John Fields]

On Mon, 17 Jan 2005 22:38:14 +0000 (UTC), weingart@cs.ualberta.ca
(Tobias Weingartner) wrote:

I'm looking for some way to figure out a circuit that will lock onto
a signal (0-5v, binary) in such a way that no matter what the current
frequency of the input signal (ok, within reason, 720 p/s to 21600 p/s),
the output signal would be 100 times the input frequency.

In other words, I'd like to have 50 equally spaced pulses occur between
consecutive transitions of the input signal?

---
It can't be done exactly if you don't know when the next transition
will occur.

--
John Fields

 

[mike]

Tobias Weingartner wrote:

I'm looking for some way to figure out a circuit that will lock onto
a signal (0-5v, binary) in such a way that no matter what the current
frequency of the input signal (ok, within reason, 720 p/s to 21600 p/s),
the output signal would be 100 times the input frequency.

In other words, I'd like to have 50 equally spaced pulses occur between
consecutive transitions of the input signal?

Might be helpful to describe what you're trying to accomplish.
What you're asking is probably impossible in the general case.
But there may well be techiniques to solve your overall problem.

Wasn't there a song about that?
mike

--
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[Ken Smith]

In article <slrncuofin.pe4.weingart@irricana.cs.ualberta.ca>,
Tobias Weingartner <weingart@cs.ualberta.ca> wrote:

I'm looking for some way to figure out a circuit that will lock onto
a signal (0-5v, binary) in such a way that no matter what the current
frequency of the input signal (ok, within reason, 720 p/s to 21600 p/s),
the output signal would be 100 times the input frequency.

In other words, I'd like to have 50 equally spaced pulses occur between
consecutive transitions of the input signal?

It sounds like you want a frequency multiplying Phase Lock Loop. Look at
the app. notes on the CD4046.

--
--
kensmith@rahul.net forging knowledge

 

[Sylvan Butler]

On Mon, 17 Jan 2005 22:38:14 +0000 (UTC), Tobias Weingartner <weingart@cs.ualberta.ca> wrote:

I'm looking for some way to figure out a circuit that will lock onto
a signal (0-5v, binary) in such a way that no matter what the current
frequency of the input signal (ok, within reason, 720 p/s to 21600 p/s),
the output signal would be 100 times the input frequency.

In other words, I'd like to have 50 equally spaced pulses occur between
consecutive transitions of the input signal?

How fast a lock (in terms of input cycles) before the output reflects
100x input?

How fast/often does the input frequency change?

If the answer to the first is >3 cycles, and the answer to the second is
not too often, then you could probably do it with a microcontroller.
720hz to 22khz is not very fast. Microcontroller could measure a cycle
or two of input, and start producing 100x output pulses. Some have
hardware that would help, but with speeds that slow, if the tolerance is
fairly low, should be no problem with modern microcontroller speeds even
entirely in software.

sdb

--
Wanted: Omnibook 800 & accessories, cheap, working or not
sdbuse1 on mailhost bigfoot.com

 

[Rich Grise]

On Mon, 17 Jan 2005 15:36:20 -0800, mike wrote:

Tobias Weingartner wrote:
I'm looking for some way to figure out a circuit that will lock onto
a signal (0-5v, binary) in such a way that no matter what the current
frequency of the input signal (ok, within reason, 720 p/s to 21600 p/s),
the output signal would be 100 times the input frequency.

In other words, I'd like to have 50 equally spaced pulses occur between
consecutive transitions of the input signal?


Might be helpful to describe what you're trying to accomplish.
What you're asking is probably impossible in the general case.
But there may well be techiniques to solve your overall problem.

Wasn't there a song about that?

Ah, there's nothing to it. A VCO that goes from 720KHz to 2.16MHz, a
divide-by-100 counter, and a phase comparator. IOW, PLL.

The OP should do a web search on "Phase-locked loop".

Cheers!
Rich

 

[Don Lancaster]

John Fields wrote:

On Mon, 17 Jan 2005 22:38:14 +0000 (UTC), weingart@cs.ualberta.ca
(Tobias Weingartner) wrote:

I'm looking for some way to figure out a circuit that will lock onto
a signal (0-5v, binary) in such a way that no matter what the current
frequency of the input signal (ok, within reason, 720 p/s to 21600 p/s),
the output signal would be 100 times the input frequency.

In other words, I'd like to have 50 equally spaced pulses occur between
consecutive transitions of the input signal?

---
It can't be done exactly if you don't know when the next transition
will occur.

--
John Fields

And the problem with a CMOS 4046 PLL would be....?

--
Many thanks,

Don Lancaster
Synergetics 3860 West First Street Box 809 Thatcher, AZ 85552
voice: (928)428-4073 email: don@tinaja.com

Please visit my GURU's LAIR web site at http://www.tinaja.com

 

[Ken Smith]

In article <41EDB245.6F1606BD@tinaja.com>,
Don Lancaster <don@tinaja.com> wrote:

John Fields wrote:

On Mon, 17 Jan 2005 22:38:14 +0000 (UTC), weingart@cs.ualberta.ca
(Tobias Weingartner) wrote:

I'm looking for some way to figure out a circuit that will lock onto
a signal (0-5v, binary) in such a way that no matter what the current
frequency of the input signal (ok, within reason, 720 p/s to 21600 p/s),
the output signal would be 100 times the input frequency.
[...]
And the problem with a CMOS 4046 PLL would be....?

21600 * 100 = 2160000 IIRC you can't do 2MHz with a CD4046 at 5V

Use a HC4046.



--
--
kensmith@rahul.net forging knowledge

 

[Mark Jones]

Ken Smith wrote:

In article <41EDB245.6F1606BD@tinaja.com>,
Don Lancaster <don@tinaja.com> wrote:

John Fields wrote:

On Mon, 17 Jan 2005 22:38:14 +0000 (UTC), weingart@cs.ualberta.ca
(Tobias Weingartner) wrote:


I'm looking for some way to figure out a circuit that will lock onto
a signal (0-5v, binary) in such a way that no matter what the current
frequency of the input signal (ok, within reason, 720 p/s to 21600 p/s),
the output signal would be 100 times the input frequency.

[...]

And the problem with a CMOS 4046 PLL would be....?


21600 * 100 = 2160000 IIRC you can't do 2MHz with a CD4046 at 5V

Use a HC4046.

Kinda OT, but if you've got OpenOffice installed, I'm working on an
alpha version of a 4046 spreadsheet VCO calculator. (Disregard the
scribbles, it's a work-in-progress...) If you can't see the image, you
enter Vdd, R1, R2, and C1 and it calculates Max,Center, and Minimum
VCO frequency. A separate section takes Vdd, fMax, fMin, and C1 and
gives R1, R2, and maxium Id.
http://groups.yahoo.com/group/jallist/files/heliosstudios/4046CalcRevA0.4.png

 

[Clive Tobin]

Only use a National (Fairchild now?) 74HC4046 or maybe a Motorola (ON
now?) 74HC4046. The former RCA version (whatever brand they are called
now, I can't keep up with it) 74HC4046A has a VCO that only works over
a narrow frequency range. The National and Motorola ones are not
directly interchangeable as they call for different oscillator
component values but they will reach 5 MHz.

 

[Ken Smith]

In article <1106105475.620295.58100@c13g2000cwb.googlegroups.com>,
Clive Tobin <clive@webband.com> wrote:

Only use a National (Fairchild now?) 74HC4046 or maybe a Motorola (ON
now?) 74HC4046. The former RCA version (whatever brand they are called
now, I can't keep up with it) 74HC4046A has a VCO that only works over
a narrow frequency range. The National and Motorola ones are not
directly interchangeable as they call for different oscillator
component values but they will reach 5 MHz.

I know from experience that some HC4046s will go to 20MHz when the Vc pin
is at Vcc. They do so with a very non-linear jump near the top of the
span.

None of the 4046 product lines really interchange well. It is best to
either specify one maker or make your circuit sloppy enough to handle the
difference between 2 makers.



--
--
kensmith@rahul.net forging knowledge

 

[Mark Jones]

Ken Smith wrote:

In article <tqCdnQr7CPSZW3DcRVn-hA@buckeye-express.com>,
Mark Jones <abuse@127.0.0.1> wrote:
[...]

Kinda OT, but if you've got OpenOffice installed, I'm working on an
alpha version of a 4046 spreadsheet VCO calculator. (Disregard the
scribbles, it's a work-in-progress...) If you can't see the image, you
enter Vdd, R1, R2, and C1 and it calculates Max,Center, and Minimum
VCO frequency. A separate section takes Vdd, fMax, fMin, and C1 and
gives R1, R2, and maxium Id.
http://groups.yahoo.com/group/jallist/files/heliosstudios/4046CalcRevA0.4.png


My Yahoo groups access seems to be on vacation today.

Based on your discription I'm assuming you didn't include the following.

You should also include the effects of hooking R1 and R2 to slightly
positive voltages. (Yes, I have done this for a good reason)

That's a good idea. I've been designing it based around the formulas
found in a CMOS 4046 datasheet, which exact model I forget at the
moment. Any chance you'd know how R1&R2 voltage affects frequency
(mathmatically?)

The stray capacitance on the capacitors leads lowers the frequency
slightly. A method to insert this may be nice.

Good point.

Also, did you know that different makers 4046 work slightly different near
the ends of the control range? This makes non-sense of any general
program when the ends of the travel are involved. You should warn of
this.

So it seems! How counter-intuitive.

Thanks.

 

[Ken Smith]

In article <aIKdnTObZ4OBAHPcRVn-tw@buckeye-express.com>,
Mark Jones <abuse@127.0.0.1> wrote:

Ken Smith wrote:
In article <tqCdnQr7CPSZW3DcRVn-hA@buckeye-express.com>,
[...]
You should also include the effects of hooking R1 and R2 to slightly
positive voltages. (Yes, I have done this for a good reason)



That's a good idea. I've been designing it based around the formulas
found in a CMOS 4046 datasheet, which exact model I forget at the
moment. Any chance you'd know how R1&R2 voltage affects frequency
(mathmatically?)

Both parts feed current mirror circuits inside the chip. The slight
positive voltage subtracts from the voltage across the resistor and thus
reduces the current in a nearly linear manner.


--
--
kensmith@rahul.net forging knowledge

 

[Tobias Weingartner]

In article <csmcgh$j0s$3@blue.rahul.net>, Ken Smith wrote:

In article <slrncutapu.1u8.weingart@irricana.cs.ualberta.ca>,
Tobias Weingartner <weingart@cs.ualberta.ca> wrote:
[...]
Take a high frequency signal, say 16MHz, and count the pulses for each
high/low part of the signal. Use the last 3 to get an idea (average and
direction) of where the signal is going, and use that as the prediction
for how many 16MHz pulses will be in the current high/low of the input
signal. With a little math, I can get close enough to the angular postion
I'm interested in. (Yes, it has to be real-time, no delay). However,
this seemed very fpga/cpld real-estate expensive, given that it would
likely involve a single cycle divide of some fairly wide bit-bus.

You are in luck: I think it can all be done with pre-setting counters. You
shouldn't really need a divide. What calculation did you intend to do?

Well, let's say that I use a 16MHz clock, and count how many clock cycles
each cycle of the input signal takes. When the encoder is moving slowly,
it may be several thousands of the 16MHz clock. When the encoder is moving
slower, it may only be a few hundred. I want to fire when a certain angular
point is reached (down to a 0.1 degree resolution). Note that the angular
firing position is not static either, it maybe 36.4 degrees one time, and
37.1 degrees the next time around.

--
[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

 

[Tobias Weingartner]

Tobias Weingartner wrote:

Well, let's say that I use a 16MHz clock, and count how many clock cycles
each cycle of the input signal takes. When the encoder is moving slowly,
it may be several thousands of the 16MHz clock. When the encoder is moving
slower, it may only be a few hundred. I want to fire when a certain angular
point is reached (down to a 0.1 degree resolution). Note that the angular
firing position is not static either, it maybe 36.4 degrees one time, and
37.1 degrees the next time around.

I think a PLL of sorts is the way I'm going to go. Right now I'm
investigating FPGA and digital PLL's. Thank you guys for pointing
me in the right direction.

--
[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

 

[Tobias Weingartner]

Pig Bladder wrote:

On Wed, 19 Jan 2005 20:19:07 +0000, Tobias Weingartner wrote:

Well, let's say that I use a 16MHz clock, and count how many clock cycles
each cycle of the input signal takes. When the encoder is moving slowly,
^^^^^^
it may be several thousands of the 16MHz clock. When the encoder is
^^^^^^^^^
moving slower, it may only be a few hundred.
^^^^^^ ^^^^^^^

I think you might be better served to learn the difference between "UP"
and "DOWN".

*chuckle*

I was wondering if I had mis-typed the above. Reading it again it seems
that I did not. When the encoder is rotating slowly, the pulses come far
appart (in terms of time), therefore a lot more of the 16MHz clock pulses
would fit between each pulse from the encoder. If the encoder is moving
fast(er), a lot less pulses from the 16MHz clock would be able to fit
between the pulses of the encoder output.


More clear?

--
[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

 

[Tobias Weingartner]

Tobias Weingartner wrote:

I'm looking for some way to figure out a circuit that will lock onto
a signal (0-5v, binary) in such a way that no matter what the current
frequency of the input signal (ok, within reason, 720 p/s to 21600 p/s),
the output signal would be 100 times the input frequency.

In other words, I'd like to have 50 equally spaced pulses occur between
consecutive transitions of the input signal?

I'm following up to my post to give more information. Basically, I
wish to "enhance" the resolution of a rotary encoder. I could do this
in the following way:

Take a high frequency signal, say 16MHz, and count the pulses for each
high/low part of the signal. Use the last 3 to get an idea (average and
direction) of where the signal is going, and use that as the prediction
for how many 16MHz pulses will be in the current high/low of the input
signal. With a little math, I can get close enough to the angular postion
I'm interested in. (Yes, it has to be real-time, no delay). However,
this seemed very fpga/cpld real-estate expensive, given that it would
likely involve a single cycle divide of some fairly wide bit-bus.

The hc4046 suggestion sounds interesting. I'll read some more on this
beast and see if I can understand it.


The ideal circuit would look something like this:


Encoder
Output -------
--|__|--| --> | C |-- \
| i |-- \
| r | . \
| c | . =-> 13 or 14 bit parallel position output
| u | . /
| i |-- /
| t |-- /
|-----|

Part of this circuit (the part to the right of the above definitely)
will be implemented on an FPGA. So I was hoping there was an easy
way to "multiply" the encoder output to 10x, feed that into counters
of sorts (I need to match certain pulse counts, and trigger events in
real-time according to these pulse counts).

--
[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

 

[Ken Smith]

In article <slrncutapu.1u8.weingart@irricana.cs.ualberta.ca>,
Tobias Weingartner <weingart@cs.ualberta.ca> wrote:
[...]

Take a high frequency signal, say 16MHz, and count the pulses for each
high/low part of the signal. Use the last 3 to get an idea (average and
direction) of where the signal is going, and use that as the prediction
for how many 16MHz pulses will be in the current high/low of the input
signal. With a little math, I can get close enough to the angular postion
I'm interested in. (Yes, it has to be real-time, no delay). However,
this seemed very fpga/cpld real-estate expensive, given that it would
likely involve a single cycle divide of some fairly wide bit-bus.

You are in luck: I think it can all be done with pre-setting counters. You
shouldn't really need a divide. What calculation did you intend to do?

The hc4046 suggestion sounds interesting. I'll read some more on this
beast and see if I can understand it.

The type-2 phase comparitor is the one you want.


--
--
kensmith@rahul.net forging knowledge

 

[John Fields]

On Tue, 18 Jan 2005 18:05:09 -0700, Don Lancaster <don@tinaja.com>
wrote:

John Fields wrote:

On Mon, 17 Jan 2005 22:38:14 +0000 (UTC), weingart@cs.ualberta.ca
(Tobias Weingartner) wrote:

I'm looking for some way to figure out a circuit that will lock onto
a signal (0-5v, binary) in such a way that no matter what the current
frequency of the input signal (ok, within reason, 720 p/s to 21600 p/s),
the output signal would be 100 times the input frequency.

In other words, I'd like to have 50 equally spaced pulses occur between
consecutive transitions of the input signal?

---
It can't be done exactly if you don't know when the next transition
will occur.

--
John Fields

And the problem with a CMOS 4046 PLL would be....?

---
The problem wouldn't be with the 4046, necessarily, it would be with
the concept of trying to stuff a given number of equally spaced pulses
into a time slot of an unknown duration.

--
John Fields

 

[Pig Bladder]

On Wed, 19 Jan 2005 20:19:07 +0000, Tobias Weingartner wrote:

In article <csmcgh$j0s$3@blue.rahul.net>, Ken Smith wrote:
In article <slrncutapu.1u8.weingart@irricana.cs.ualberta.ca>,
Tobias Weingartner <weingart@cs.ualberta.ca> wrote:
[...]
Take a high frequency signal, say 16MHz, and count the pulses for each
high/low part of the signal. Use the last 3 to get an idea (average and
direction) of where the signal is going, and use that as the prediction
for how many 16MHz pulses will be in the current high/low of the input
signal. With a little math, I can get close enough to the angular postion
I'm interested in. (Yes, it has to be real-time, no delay). However,
this seemed very fpga/cpld real-estate expensive, given that it would
likely involve a single cycle divide of some fairly wide bit-bus.

You are in luck: I think it can all be done with pre-setting counters. You
shouldn't really need a divide. What calculation did you intend to do?

Well, let's say that I use a 16MHz clock, and count how many clock cycles
each cycle of the input signal takes. When the encoder is moving slowly,
^^^^^^
it may be several thousands of the 16MHz clock. When the encoder is
^^^^^^^^^
moving slower, it may only be a few hundred.
^^^^^^ ^^^^^^^

I think you might be better served to learn the difference between "UP"
and "DOWN".
--
The Pig Bladder From Uranus, Still Waiting for
Some Hot Babe to Ask What My Favorite Planet Is.