How to decide the stages of a pipeline device?

[Cuthbert]

Good day, everyone,

Is there any basic principles for designing a pipeline device or
does anybody know books or papers I can look into it? Thanks in
advance.


Cuthbert

 

[Mike Treseler]

Cuthbert wrote:

Is there any basic principles for designing a pipeline device or
does anybody know books or papers I can look into it? Thanks in
advance.

It's more of a clocked design style than a device;
a set of parallel shift registers with logic at each node.
The trick is to line up the outputs.
See http://en.wikipedia.org/wiki/Pipeline_%28computing%29
Synthesis can do some of the work if you turn on
register retiming.

-- Mike Treseler

 

[glen herrmannsfeldt]

Cuthbert wrote:

Is there any basic principles for designing a pipeline device or
does anybody know books or papers I can look into it? Thanks in
advance.

It depends somewhat, but there is some literature for
"systolic array" processors that should help.

There are also books on pipelined computers from some
years ago that might also be useful.

-- glen

 

[Cuthbert]

Thank you for your help.

Cuthbert

On Jul 30, 12:30 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu>
wrote:

Cuthbert wrote:
Is there any basic principles for designing a pipeline device or
does anybody know books or papers I can look into it? Thanks in
advance.

It depends somewhat, but there is some literature for
"systolic array" processors that should help.

There are also books on pipelined computers from some
years ago that might also be useful.

-- glen

 

[kit]

On Jul 30, 11:41 pm, Cuthbert <cuthbert....@gmail.com> wrote:

Thank you for your help.

Cuthbert

On Jul 30, 12:30 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu
wrote:

Cuthbert wrote:
    Is there any basic principles for designing a pipeline device or
does anybody know books or papers I can look into it? Thanks in
advance.

It depends somewhat, but there is some literature for
"systolic array" processors that should help.

There are also books on pipelined computers from some
years ago that might also be useful.

-- glen

Hi,

Here is a very crude formula, mostly for academic purposes, which
might be of some use to you in your understanding:

Latency >= NS(C2Q) + NS(Input Setup) + (Logic Delay/NS) + 2 (Skew)

Latency = Cycle Time or Freq of operation;
NS => Number of stages;
And it is obvious that I have considered the worst skew.

All the best.

Krishna Praveen M. R.