How to debug suspected driver conflict?

[Andrew FPGA]

Hi,
I have a signal in my simulation of type std_logic and for the first
several hundred ns or so it appears as 'X' in modelsim. There are
multiple drivers for this signal and most drive 'z' right from 0ns so I
don't understand why I see 'x' in modelsim.

I tried the "drivers" modelsim command to help me: (this was at 0ns)

drivers cpuaddrdata(0)
# Drivers for /odslhornettoptb/cpuaddrdata(0):
# U : Signal /odslhornettoptb/cpuaddrdata(0)
# Z : Driver /odslhornettoptb/dsl1_cpu_bus_model
# Z : Driver /odslhornettoptb/dsl0_cpu_bus_model
# Z : Driver /odslhornettoptb/dut_odslhornettop/drive_data_bus
# U : Driver /odslhornettoptb/main
#

Which I interpret as one driver is uninitialised, and the rest are
driving Z. I looked up the resolution table in std_logic_1164 and to me
it says that if any one of the drivers is U then the resolved signal is
U. Yet modelsim gives me an X?

Sigh. Have figured it out. My std_logic signal was actually part of a
std_logic_vector - modelsim displays 'X' even when all of the
individual elements of the std_logic_vector were 'u'.
Well, will post anyhow, maybe this is useful to somone...