How to create verilog FF with level-sensitive reset?

B

BAC

Guest
I'm new to verilog coming from VHDL and trying to code a synthesizable
flip flop where the reset has presidence over the clock and the
reset is level-sensitive rather than edge sensitive.

In other words, what is the verilog equivalent to the common VHDL:


p_example : process( nRST, clk )
begin
if ( nRST = '0' ) then
output <= '0';
elsif rising_edge( clk ) then
output <= data;
end if;
end process;


Several books suggest this verilog for an asynchronous reset:


always @( negedge nRST, posedge clk )
if ( ! nRST )
output <= 0
else
output <= data;


But this, if I understand correctly, will only preform the reset if its
level actually changes ( from high to low ) because the 'always' statement
is only sensitive to edges.

This is for Cyclone II and Quartus but I doubt that this it matters.


Thanks.
 
In article <b%vjk.9108$L_.2593@flpi150.ffdc.sbc.com>, Bill Warner wrote:
All the flops in our ASICs are written like this:

always @( posedge clk or negedge nRST )
begin
if ( ! nRST )
output <= 0;
else
output <= data;
end

This does the right thing in synthesis, and (mostly) in simulation; the
possible exception is at beginning of simulation - if there's no falling
edge on nRST it might not get reset. We've never felt a need to model
a true "level sensitive" reset that functions even in the absence of a
transition. The main advantage would be in simulation, not synthesis.

-- Bill
Click to expand...

Thanks for the response. The code I need to write should also work fine
without true level-sensitive logic. I just wanted to be sure that this
is indeed the accepted "correct way" in verilog and that I was not
missing something fundamental about the language.

Thanks
-Ben
 
In article <20080729082036.7fcb2004@wolfenstein.jpl.nasa.gov>, Jason Zheng wrote:
On Tue, 29 Jul 2008 00:28:30 GMT
BAC <usenet08@neanderthal-design.c.o.m> wrote:

always @( negedge nRST, posedge clk )
if ( ! nRST )
output <= 0
else
output <= data;


But this, if I understand correctly, will only preform the reset if
its level actually changes ( from high to low ) because the 'always'
statement is only sensitive to edges.


This code indeed creates a level-sensitive reset FF. Keep in mind that
even without nRST falling, rising edge of the clock also triggers the
always block, and the first if clause always takes precedence over the
second one.
Click to expand...
I guess my question is: does this end up creating a real level-sensitive
reset using the real chip asynchronous reset signals in the FPGA despite
the "negedge nRST" part of the sinsitivity list? Or does this
synthesize exactly as the verilog syntax indicates such that the
effect is simply "level-sensitive like behaviour" where even if
nRST comes up low and stays low, its level will only be detected
when the next clock occurs?

Thanks
-Ben
 
always @( negedge nRST, posedge clk )
if ( ! nRST )
output <= 0
else
output <= data;


But this, if I understand correctly, will only preform the reset if its
level actually changes ( from high to low ) because the 'always' statement
is only sensitive to edges.
Click to expand...
All the flops in our ASICs are written like this:

always @( posedge clk or negedge nRST )
begin
if ( ! nRST )
output <= 0;
else
output <= data;
end

This does the right thing in synthesis, and (mostly) in simulation; the
possible exception is at beginning of simulation - if there's no falling
edge on nRST it might not get reset. We've never felt a need to model
a true "level sensitive" reset that functions even in the absence of a
transition. The main advantage would be in simulation, not synthesis.

-- Bill
 
On Tue, 29 Jul 2008 00:28:30 GMT
BAC <usenet08@neanderthal-design.c.o.m> wrote:

always @( negedge nRST, posedge clk )
if ( ! nRST )
output <= 0
else
output <= data;


But this, if I understand correctly, will only preform the reset if
its level actually changes ( from high to low ) because the 'always'
statement is only sensitive to edges.
Click to expand...
This code indeed creates a level-sensitive reset FF. Keep in mind that
even without nRST falling, rising edge of the clock also triggers the
always block, and the first if clause always takes precedence over the
second one.


--
I got this powdered water -- now I don't know what to add.
-- Steven Wright
 
On Jul 28, 11:19 pm, Bill Warner <bi...@bill-sascha.org> wrote:
always @( negedge nRST, posedge clk )
if ( ! nRST )
output <= 0
else
output <= data;

But this, if I understand correctly, will only preform the reset if its
level actually changes ( from high to low ) because the 'always' statement
is only sensitive to edges.

All the flops in our ASICs are written like this:

always @( posedge clk or negedge nRST )
begin
if ( ! nRST )
output <= 0;
else
output <= data;
end

This does the right thing in synthesis, and (mostly) in simulation; the
possible exception is at beginning of simulation - if there's no falling
edge on nRST it might not get reset. We've never felt a need to model
a true "level sensitive" reset that functions even in the absence of a
transition. The main advantage would be in simulation, not synthesis.

-- Bill
Click to expand...
Actually in simulation the only reason not to get a negative edge at
the start of simulation is that the signal remains undriven or goes
high instead, neither of which should cause a reset condition. Since
something needs to make nRST go low at time zero, usually an initial
block like:

reg nRST;
initial begin
nRST = 0;
. . . other initializations
# <some time period> nRST = 1;
end

or in the declaration like:

reg nRST = 0;

you would stll get a "negedge" on nRST at time zero when nRST goes
from
undriven (1'bZ) to zero.

Regards,
Gabor
 
On Tue, 29 Jul 2008 19:52:27 GMT
BAC <usenet08@neanderthal-design.c.o.m> wrote:

This code indeed creates a level-sensitive reset FF. Keep in mind
that even without nRST falling, rising edge of the clock also
triggers the always block, and the first if clause always takes
precedence over the second one.


I guess my question is: does this end up creating a real
level-sensitive reset using the real chip asynchronous reset signals
in the FPGA despite the "negedge nRST" part of the sinsitivity
list? Or does this synthesize exactly as the verilog syntax
indicates such that the effect is simply "level-sensitive like
behaviour" where even if nRST comes up low and stays low, its level
will only be detected when the next clock occurs?
Click to expand...
You'll have to ask yourself what's the difference between
"level-sensitive" logic and "if nRST comes up low and stays low, its
level will only be detected when the next clock occurs."

There is no functional difference between two descriptions. Your code
synthesizes to a DFF with active-low asynchronous reset. Besides the
order of edge-triggered events, your code is how a typical DFF would
have been described in Verilog. Stop thinking in VHDL when you are
writing Verilog.


--
I got this powdered water -- now I don't know what to add.
-- Steven Wright
 
BAC wrote:

I guess my question is: does this end up creating a real level-sensitive
reset using the real chip asynchronous reset signals in the FPGA despite
the "negedge nRST" part of the sinsitivity list?
Click to expand...
Yes.
Verilog can't really do an edge test.

-- Mike Treseler
 
BAC wrote:
In article <20080729082036.7fcb2004@wolfenstein.jpl.nasa.gov>, Jason Zheng wrote:
On Tue, 29 Jul 2008 00:28:30 GMT
BAC <usenet08@neanderthal-design.c.o.m> wrote:

always @( negedge nRST, posedge clk )
if ( ! nRST )
output <= 0
else
output <= data;


But this, if I understand correctly, will only preform the reset if
its level actually changes ( from high to low ) because the 'always'
statement is only sensitive to edges.


This code indeed creates a level-sensitive reset FF. Keep in mind that
even without nRST falling, rising edge of the clock also triggers the
always block, and the first if clause always takes precedence over the
second one.


I guess my question is: does this end up creating a real level-sensitive
reset using the real chip asynchronous reset signals in the FPGA despite
the "negedge nRST" part of the sinsitivity list? Or does this
synthesize exactly as the verilog syntax indicates such that the
effect is simply "level-sensitive like behaviour" where even if
nRST comes up low and stays low, its level will only be detected
when the next clock occurs?

Thanks
-Ben
Click to expand...
All synthesizers should implement the real async reset control and not
add logic to handle the situation where the reset comes up low and
stays low.

Verilog synthesis is a subset of Verilog simulation and certain
standard structures are needed to map to real silicon. The reset
structure you've shown is one of those guaranteed-to-work constructs.
 
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