How to create main file using two different verilog file..

[Verilog_Maan]

hello friends

I want to know that how we will connect two differnt file to make Main
file?I mean I want to simulate two different file together ..it is
similar to VHDL port mapping?

so can any one tell me how we do port mapping in VERILOG?

 

On Oct 23, 2:32 am, Verilog_Maan <mansipat...@gmail.com> wrote:

hello friends

I want to know that how we will connect two differnt file to make Main
file?I mean I want to simulate two different file together ..it is
similar to VHDL port mapping?

so can any one tell me how we do port mapping in VERILOG?

--
What do you have on these two different files?
Does each file containts different modules?