Guest
Hi all,
I have installed ISE Foundation (6.2.03) and tried to generate an
EDIF file from a Verilog file. I remember I could do it a few years
ago with 4.x version (not sure).
I need to install something special?
Anyway, what happens if the design has parameters? The EDIF file
allow it?
Thanks in advance, Santiago.
I have installed ISE Foundation (6.2.03) and tried to generate an
EDIF file from a Verilog file. I remember I could do it a few years
ago with 4.x version (not sure).
I need to install something special?
Anyway, what happens if the design has parameters? The EDIF file
allow it?
Thanks in advance, Santiago.