How to create a LVPECL_25 output pair (Spartan3, ISE 9.1)

[Thomas Heller]

I'm trying to create a LVPECL_25 differential output on a Spartan 3
(XC3S200 device in PQ208 package). I did this by selecting 'LVPECL_25'
in the I/O Standard column in PACE (assign package pins).

However, in 'Implement Design' I get the following error:

Process "Translate" completed successfully
Using target part "3s200pq208-5".
Mapping design into LUTs...
Running directed packing...
ERRORack:946 - The I/O component "q" has an illegal IOSTANDARD value.
Components of type IOB do not support IOSTANDARD LVPECL_25. Please correct
the IOSTANDARD property value.


What am I doing wrong? I'm still using ISE 9.1.03i.

Thanks,
Thomas

 

[John_H]

On Jul 21, 3:23 pm, Thomas Heller <thel...@python.net> wrote:

I'm trying to create a LVPECL_25 differential output on a Spartan 3
(XC3S200 device in PQ208 package).  I did this by selecting 'LVPECL_25'
in the I/O Standard column in PACE (assign package pins).

However, in 'Implement Design' I get the following error:

Process "Translate" completed successfully
Using target part "3s200pq208-5".
Mapping design into LUTs...
Running directed packing...
ERRORack:946 - The I/O component "q" has an illegal IOSTANDARD value.
   Components of type IOB do not support IOSTANDARD LVPECL_25.  Please correct
   the IOSTANDARD property value.

What am I doing wrong?  I'm still using ISE 9.1.03i.

Thanks,
Thomas

Type IOB? Do you mean Type IOBUF? If it's the latter, the
differential version might be IOBUFDS.

I took a look at Table 10-3: Spartan-3 Generation I/O Components on
page 321 of UG331 (v1.6) Spartan-3 Generation
FPGA User Guide - http://www.xilinx.com/support/documentation/user_guides/ug331.pdf
- where some of the implementation details might be less murky.

 

[Thomas Heller]

John_H schrieb:

On Jul 21, 3:23 pm, Thomas Heller <thel...@python.net> wrote:
I'm trying to create a LVPECL_25 differential output on a Spartan 3
(XC3S200 device in PQ208 package). I did this by selecting 'LVPECL_25'
in the I/O Standard column in PACE (assign package pins).

However, in 'Implement Design' I get the following error:

Process "Translate" completed successfully
Using target part "3s200pq208-5".
Mapping design into LUTs...
Running directed packing...
ERRORack:946 - The I/O component "q" has an illegal IOSTANDARD value.
Components of type IOB do not support IOSTANDARD LVPECL_25. Please correct
the IOSTANDARD property value.

What am I doing wrong? I'm still using ISE 9.1.03i.

Thanks,
Thomas

Type IOB? Do you mean Type IOBUF? If it's the latter, the
differential version might be IOBUFDS.

I took a look at Table 10-3: Spartan-3 Generation I/O Components on
page 321 of UG331 (v1.6) Spartan-3 Generation
FPGA User Guide - http://www.xilinx.com/support/documentation/user_guides/ug331.pdf
- where some of the implementation details might be less murky.

Well, the problem was that I have to instantiate an OBUFDS explicitely;
then I could set the IOSTANDARD attribute:

OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "LVPECL_25")
port map (
O => o, -- Diff_p output (connect directly to top-level port)
OB => o_not, -- Diff_n output (connect directly to top-level port)
I => count(3) -- Buffer input
);

Thanks,
Thomas