How to create a directory in VHDL Simulation

[Benjamin Couillard]

Hi everyone,

Out of curiosity, I was wondering if there is a way to create a
directory in VHDL? I can create files with the WRITE procedure.
However, this procedure will not work if the directory specified does
not exist so I was wondering if there was a way in VHDL itself to
create the missing directory.

Best regards

 

[Jonathan Bromley]

On Sep 16, 3:33 pm, Benjamin Couillard wrote:

Out of curiosity, I was wondering if there is a way to create a
directory in VHDL? I can create files with the WRITE procedure.
However, this procedure will not work if the directory specified does
not exist so I was wondering if there was a way in VHDL itself to
create the missing directory.

Nothing in the language or its standard libraries, no.
There may be vendor extensions to do it, and you can do
it through VHPI/FLI/DirectC or whatever foreign-language
interface is provided by your preferred simulator.

Suggestion: Don't even try it. VHDL's tools for exploring
the file system are hopeless. Instead, run the sim from a
script that first sets up all the desired input data IN THE
SIMULATOR'S WORKING DIRECTORY, with simple filenames that
you can put into your VHDL as literals. Then get the VHDL
sim to write files, with simple fixed names, IN THE
SIMULATOR'S WORKING DIRECTORY. And then, when simulation
is done, the script moves those files to a sensible place.

Scripting languages are brilliant for all this sort of
thing; VHDL is garbage for it. Use the right tool for
the job.

In a script you can also easily arrange for output log
files to have unique names based on time-of-day, for
example. Try doing that in VHDL - no, I don't think so.
--
Jonathan Bromley