How to create a delay?

[Amit]

Hi group,

I'm using Quartus II to design the control interface for Wolfson
CODEC WM873. Now, base on its timing specs:

page 18 at
http://www.wolfsonmicro.com/uploads/documents/en/WM8731.pdf


I need to make delay for SDIN . How can I create delay?!


Thanks.

 

[Mike Treseler]

Amit wrote:

I need to make delay for SDIN . How can I create delay?!

I would use a fast clock for the FPGA input and create
the Sclk *output* using a rollover variable.
Then the data setup can be adjusted
with a resolution of one fast tick.

-- Mike Treseler

 

[Dave]

On Mar 27, 2:34 am, Amit <amit.ko...@gmail.com> wrote:

Hi group,

I'm using Quartus II to design the control interface for Wolfson
CODEC WM873. Now, base on its timing specs:

page 18 athttp://www.wolfsonmicro.com/uploads/documents/en/WM8731.pdf

I need to make delay for SDIN . How can I create delay?!

Thanks.

Depending on your clock rate, clocking SDIN on the falling edge of SCK
might help. Also, some FPGA's have tapped delay elements in the pads
that might help you out.

 

[David Spencer]

"Amit" <amit.kohan@gmail.com> wrote in message
news:bd2b8e80-8003-405f-bf63-a92f1091ce0a@c19g2000prf.googlegroups.com...

Hi group,

I'm using Quartus II to design the control interface for Wolfson
CODEC WM873. Now, base on its timing specs:

page 18 at
http://www.wolfsonmicro.com/uploads/documents/en/WM8731.pdf


I need to make delay for SDIN . How can I create delay?!


Thanks.

By far the easiest way is to start with a clock at twice the speed of SCLK
and just divide this using a flip-flop to generate SCLK itself. You can then
clock the logic that generates SDIN from the fast clock, but use SCLK as an
active-high clock enable. This will ensure that SDIN only changes at the
same time as SCLK goes from high to low, which gives you a whole half an
SCLK cycle setup and hold time.


Incidentally, we don't mind helping you out with tricky problems, but this
really is a basic design task.

 

[Amit]

On Mar 27, 9:37 am, "David Spencer" <davidmspen...@verizon.net> wrote:

"Amit" <amit.ko...@gmail.com> wrote in message

news:bd2b8e80-8003-405f-bf63-a92f1091ce0a@c19g2000prf.googlegroups.com...



Hi group,

I'm using Quartus II to design the control interface for Wolfson
CODEC WM873. Now, base on its timing specs:

page 18 at
http://www.wolfsonmicro.com/uploads/documents/en/WM8731.pdf

I need to make delay for SDIN . How can I create delay?!

Thanks.

By far the easiest way is to start with a clock at twice the speed of SCLK
and just divide this using a flip-flop to generate SCLK itself. You can then
clock the logic that generates SDIN from the fast clock, but use SCLK as an
active-high clock enable. This will ensure that SDIN only changes at the
same time as SCLK goes from high to low, which gives you a whole half an
SCLK cycle setup and hold time.

Incidentally, we don't mind helping you out with tricky problems, but this
really is a basic design task.

Thanks for your comments. I believe I'm not getting something here and
yes it must be easier than what I think. As you see, when SCLK goes
from high to low the SDIN goes changes too but there must be a 20ns
(at least). I'm not sure how to cause this delay in VHDL using
Quartus. How really this should be?

Thanks.

 

[Symon]

Amit wrote:

Thanks for your comments. I believe I'm not getting something here and
yes it must be easier than what I think. As you see, when SCLK goes
from high to low the SDIN goes changes too but there must be a 20ns
(at least). I'm not sure how to cause this delay in VHDL using
Quartus. How really this should be?

Thanks.

Hi Amit,

No, that's not what the diagram says. It says that SDIN must be stable 20ns
before the rising edge of SCLK. This is the 'setup time', Tsu. Then, SDIN
must stay stable for 20 ns following this rising edge. This is the 'hold
time', Tdho.

Just clock the data out at the same time as the falling edge of SCLK. Piece
of cake.

HTH., Syms.

p.s. No big deal, but this thread is a little off topic for comp.lang.vhdl.
Maybe you could try sci.electronics next time?

 

[Amit]

On Mar 28, 4:07 am, "Symon" <symon_bre...@hotmail.com> wrote:

Amit wrote:

Thanks for your comments. I believe I'm not getting something here and
yes it must be easier than what I think. As you see, when SCLK goes
from high to low the SDIN goes changes too but there must be a 20ns
(at least). I'm not sure how to cause this delay in VHDL using
Quartus. How really this should be?

Thanks.

Hi Amit,

No, that's not what the diagram says. It says that SDIN must be stable 20ns
before the rising edge of SCLK. This is the 'setup time', Tsu. Then, SDIN
must stay stable for 20 ns following this rising edge. This is the 'hold
time', Tdho.

Just clock the data out at the same time as the falling edge of SCLK. Piece
of cake.

HTH., Syms.

p.s. No big deal, but this thread is a little off topic for comp.lang.vhdl..
Maybe you could try sci.electronics next time?

Hi Symon,

Thanks! please correct me if I"m wrong. I will get a clock (50Mhz) as
input + Resest_n
Then will divide the clock to 25Mhz (which will be SCLK) and base on
SCLK I must control SDIN output. Right?

One thing I didn't get. Do I need to post these qeusetion on
sci.electroncis group?! if so, then I didn't find any VHDL question
there and as far as I understand this
group is for VHDL right?!!!


Thanks.