How to convert VHDL / Verilog code to layout?

B

boki

Guest
Hi, All:

Could you please tell me or give me some hint to convert VHDL /
Verilog code to layout?.

Thanks a lot!

Boki.
 
In a nutshell:
o Run synthesis
o floorplanning
o timing analysis
o library create
o formal verification
o place & route / Clock
o signal integrity
o Design for Test
o Extraction
o DRC/LVS
o Tape-out (priceless!!!!)

--
sincerely,

Russell Powell






"boki" <bokiteam@ms21.hinet.net> wrote in message
news:4c3c095a.0402020853.6b45c9f6@posting.google.com...
Hi, All:

Could you please tell me or give me some hint to convert VHDL /
Verilog code to layout?.

Thanks a lot!

Boki.
Click to expand...
 
Thank you very much.

Boki.


"Russ" <powell270@comcast.net> wrote in message news:<_ExTb.162088$Rc4.1266576@attbi_s54>...
In a nutshell:
o Run synthesis
o floorplanning
o timing analysis
o library create
o formal verification
o place & route / Clock
o signal integrity
o Design for Test
o Extraction
o DRC/LVS
o Tape-out (priceless!!!!)

--
sincerely,

Russell Powell






"boki" <bokiteam@ms21.hinet.net> wrote in message
news:4c3c095a.0402020853.6b45c9f6@posting.google.com...
Hi, All:

Could you please tell me or give me some hint to convert VHDL /
Verilog code to layout?.

Thanks a lot!

Boki.
Click to expand...
 
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