How to convert Verilog to VHDL?

Hi,
Does anyone know how I can convert my verilog code to VHDL?

Stanley

 

[Andy Peters]

<liying.chang@verizon.net> wrote in message news:<yWYob.63946$1C5.22696@nwrdny02.gnilink.net>...

Hi,
Does anyone know how I can convert my verilog code to VHDL?

Ummm, by hand?

-a

 

[Kim Hyun-Gyu]

by hand
another way is using EDA tools likes Visual HDL and HDL Designer's Serise.
(and synthesis tools can export vhdl netlist from verilog RTL)


<liying.chang@verizon.net> wrote in message
news:yWYob.63946$1C5.22696@nwrdny02.gnilink.net...

Hi,
Does anyone know how I can convert my verilog code to VHDL?

Stanley

 

[Alexander Gnusin]

The main question is: do we want conversion on RTL or Gate levels?
For RTL, I completely agree that "by hand" approach is the safest one.
For gatelevel, just dump your design to vhdl format after running
synthesis, or load your verilog gatelevel to the synthesis tool and
then save it in vhdl format.

Regards,
Alexander

"Kim Hyun-Gyu" <babyworm@adc.co.kr.NOSPAM> wrote in message news:<bo73sp$khq$1@news.elim.net>...

by hand
another way is using EDA tools likes Visual HDL and HDL Designer's Serise.
(and synthesis tools can export vhdl netlist from verilog RTL)


liying.chang@verizon.net> wrote in message
news:yWYob.63946$1C5.22696@nwrdny02.gnilink.net...
Hi,
Does anyone know how I can convert my verilog code to VHDL?

Stanley