How to constrain a divide by 3 clock?

[Kelvin]

Hi, there:

My clk_4m is generated from clk_12m through a divide_by_3 state machine...
And I feed clk_4m into a BUFG also...I estimate the time from rising edge of
clk_12m to clk_4m is 3.6 ns...Can I write these two constraints?

NET "clk_12m" TNM = "clk_12m";
TIMESPEC "TS_clk_12m" = PERIOD "clk_12m" 83.3 ns HIGH 50 %;
NET "clk_4m" TNM = "clk_4m";
TIMESPEC "TS_clk_4m" = PERIOD "clk_4m" TS_clk_12m / 3 PHASE + 3.6 ns;

Thanks.
Kelvin

 

[Peter Alfke]

Kelvin, if for some reason you decide not to use a DCM to do the frequency
division, you can do this with two flip-flops and their two LUTs.
The input clock to output Q is exactly one "clock-to-Q" parameter. There can
be only one result, unless you insist on doing something weird and
non-synchonous..

Peter Alfke, Xilinx Applications

From: "Kelvin" <student@nowhere.com>
Organization: StarHub Internet Pte Ltd
Newsgroups: comp.arch.fpga
Date: Thu, 8 Jul 2004 15:45:54 +0800
Subject: How to constrain a divide by 3 clock?


Hi, there:

My clk_4m is generated from clk_12m through a divide_by_3 state machine...
And I feed clk_4m into a BUFG also...I estimate the time from rising edge of
clk_12m to clk_4m is 3.6 ns...Can I write these two constraints?

NET "clk_12m" TNM = "clk_12m";
TIMESPEC "TS_clk_12m" = PERIOD "clk_12m" 83.3 ns HIGH 50 %;
NET "clk_4m" TNM = "clk_4m";
TIMESPEC "TS_clk_4m" = PERIOD "clk_4m" TS_clk_12m / 3 PHASE + 3.6 ns;
Thanks.
Kelvin

 

[Kelvin]

Re: How to constrain a divide by 3 clock?I don't have much of a choice as those crappy oddballs here wrote all those weird RTL codes...
I am only trying to somehow put their odd eggs into the FPGA.

Is my time specifications ok to do the build and P&R?
I just need some formality thing to show them that I have done what the tools can do and flag 'em
a fail or pass.

Kelvin







"Peter Alfke" <peter@xilinx.com> wrote in message news:BD13115C.761D%peter@xilinx.com...
Kelvin, if for some reason you decide not to use a DCM to do the frequency division, you can do this with two flip-flops and their two LUTs.
The input clock to output Q is exactly one "clock-to-Q" parameter. There can be only one result, unless you insist on doing something weird and non-synchonous..

Peter Alfke, Xilinx Applications


From: "Kelvin" <student@nowhere.com>
Organization: StarHub Internet Pte Ltd
Newsgroups: comp.arch.fpga
Date: Thu, 8 Jul 2004 15:45:54 +0800
Subject: How to constrain a divide by 3 clock?




Hi, there:

My clk_4m is generated from clk_12m through a divide_by_3 state machine...
And I feed clk_4m into a BUFG also...I estimate the time from rising edge of
clk_12m to clk_4m is 3.6 ns...Can I write these two constraints?

NET "clk_12m" TNM = "clk_12m";
TIMESPEC "TS_clk_12m" = PERIOD "clk_12m" 83.3 ns HIGH 50 %;
NET "clk_4m" TNM = "clk_4m";
TIMESPEC "TS_clk_4m" = PERIOD "clk_4m" TS_clk_12m / 3 PHASE + 3.6 ns;
Thanks.
Kelvin