How to constain a internal generated clock in DC script?

[Enchanter]

I have a module. The clk of TOP is connected to the internal module
CLK_GEN. The output clk_div of CLK_GEN is divided by 0, 4, 8.

The clk_div is used as other internal modules input clock and the
output port of the TOP module.

I hope to know how to constain this signal in the top-down DC script?

Thanks in advance.

 

[mk]

On 10 Jan 2006 18:19:37 -0800, "Enchanter" <ensoul.magazine@gmail.com>
wrote:

I have a module. The clk of TOP is connected to the internal module
CLK_GEN. The output clk_div of CLK_GEN is divided by 0, 4, 8.

The clk_div is used as other internal modules input clock and the
output port of the TOP module.

I hope to know how to constain this signal in the top-down DC script?

you can use create_generated_clock with either -edges or -divide_by
option.