How to concatenate a string and a vector ?

[rkoul123@gmail.com]

Hi,
I am a VHDL person but need some help on a verilog item ..I hope you
can
help me on this :


I have a module where I am trying to use $readmemh to read data into
memory .
I am trying to append the name of the data file with the value of the
identifier "abc" which is a 4 bit vector . How do I do that append ?

reg [3:0] abc ;

This does not seem to work ->

$readmemh({"datfile.dat",abc} , memory);

I will greatly appreciate any help on this . Thanks.

RajK

 

[Jonathan Bromley]

On Wed, 01 Aug 2007 09:44:23 -0700, "rkoul123@gmail.com"
<rkoul123@gmail.com> wrote:

Hi,
I am a VHDL person but need some help on a verilog item ..I hope you
can
help me on this :


I have a module where I am trying to use $readmemh to read data into
memory .
I am trying to append the name of the data file with the value of the
identifier "abc" which is a 4 bit vector . How do I do that append ?

reg [3:0] abc ;

This does not seem to work -

$readmemh({"datfile.dat",abc} , memory);

When you say the "value" of the vector, do you mean you
want a 4-digit string of 0s and 1s? Or do you want a
single hex digit 0-9,A-F? Here's a hack for the latter:

reg [7:0] digit_char;
// compute digit character from 4-bit value
if (abc < 10)
digit_char = "0" + abc;
else
digit_char = "A" + abc - 10;
$readmemh( {"datfile.dat",digit_char} , memory);

Yuck.

You can also play games with the Verilog-2001 string format
functions, which would be easier if you want to do the
4-digit binary string.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[rkoul123@gmail.com]

On Aug 1, 9:56 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On Wed, 01 Aug 2007 09:44:23 -0700, "rkoul...@gmail.com"



rkoul...@gmail.com> wrote:
Hi,
I am a VHDL person but need some help on a verilog item ..I hope you
can
help me on this :

I have a module where I am trying to use $readmemh to read data into
memory .
I am trying to append the name of the data file with the value of the
identifier "abc" which is a 4 bit vector . How do I do that append ?

reg [3:0] abc ;

This does not seem to work -

$readmemh({"datfile.dat",abc} , memory);

When you say the "value" of the vector, do you mean you
want a 4-digit string of 0s and 1s? Or do you want a
single hex digit 0-9,A-F? Here's a hack for the latter:

reg [7:0] digit_char;
// compute digit character from 4-bit value
if (abc < 10)
digit_char = "0" + abc;
else
digit_char = "A" + abc - 10;
$readmemh( {"datfile.dat",digit_char} , memory);

Yuck.

You can also play games with the Verilog-2001 string format
functions, which would be easier if you want to do the
4-digit binary string.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

It works ! Thanks a lot .
You mentioned Verilog-2001 string format functions ..how would you
achieve the same using those ..an example would help me .

 

[Kevin Neilson]

rkoul123@gmail.com wrote:

Hi,
I am a VHDL person but need some help on a verilog item ..I hope you
can
help me on this :


I have a module where I am trying to use $readmemh to read data into
memory .
I am trying to append the name of the data file with the value of the
identifier "abc" which is a 4 bit vector . How do I do that append ?

reg [3:0] abc ;

This does not seem to work -

$readmemh({"datfile.dat",abc} , memory);

I will greatly appreciate any help on this . Thanks.

RajK

You might have some trouble with the tools if you do this. I did
something very similar, which should have worked. (Like Jonathan notes,
the value abc must be an ASCII value.) Srings and vectors in Verilog
shouldn't be handled differently. However, Synplify would not support
this filename manipulation. I notified them but I don't know if the
issue has been resolved. -Kevin