How to code a bus of open collector outputs

U

Uwe Bonnes

Guest
If I need some open collector signal on some IO Port, I code it like

io= (variable)?1'b0:1'bz;

How do I do this for vectors, beside breaking up like

io[0] = (variable[0])?1'b0:1'bz;
io[1] = (variable[1])?1'b0:1'bz;

Thanks
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
One way is to define an OC buffer, and do an array instantiation:

oc_buff b[15:0](.in(variable),.oc(oc));
 
I don't know about synthesis, but the natural way to do this for
simulation is by defining the drive strength on the continuous
assignment. This works for vectors or scalars:

assign (strong0, highz1) io = variable;

This makes the drive strength z when driving a 1.

Like your example, this assumes that you have an explicit pullup
instantiated somewhere. You can do this implicitly instead by
including the pullup in the driver. Just change the drive strength
when driving a 1 from highz1 to pull1 instead. Or you can go
completely abstract and just declare the net to be a wand net type,
instead of explicitly modeling the drive strengths.
 
You can use genarate

Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in news:e1e5to$vmo
$1@lnx107.hrz.tu-darmstadt.de:

If I need some open collector signal on some IO Port, I code it like

io= (variable)?1'b0:1'bz;

How do I do this for vectors, beside breaking up like

io[0] = (variable[0])?1'b0:1'bz;
io[1] = (variable[1])?1'b0:1'bz;

Thanks
 
Uwe Bonnes wrote:
If I need some open collector signal on some IO Port, I code it like

io= (variable)?1'b0:1'bz;

How do I do this for vectors, beside breaking up like

io[0] = (variable[0])?1'b0:1'bz;
io[1] = (variable[1])?1'b0:1'bz;
You can do this in a for loop, something like:

integer i;
reg [1:0] io_internal;

always @(variable)
for (i=0;i<2;i=i+1)
io_internal = variable?1'b0:1'bz;

assign io = io_internal;


Note: The above will work in verilog-95, whereas some of the suggestions
already posted are verilog-2001 only.

John

--
John Penton, posting as an individual unless specifically indicated
otherwise.
 

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