How to clear Cadence SE VERIFY GEOMETRY Viols

Y

ykjing

Guest
Hi,
In Cadence SE, after floorplanning and add power ring, I verified geometry.
There is no viols. However ,after adding power strip, there are four
Antennas Viols.

I removed the power strips and placed cells with timing driven option, there
are lots of geometry viols as flows:

16:02:15 * VERIFY GEOMETRY CPU 0 0:00:00 Sub-Area 1 of 1.. 0 Viols.
16:02:15 * VERIFY GEOMETRY CPU 0 0:00:00 Cells.. 82 Viols.
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Special Wiring.. 13 Viols
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Regular Wiring.. 0 Viols
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Same-Net.. 0 Viols.
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Same-Net.. 0 Viols.
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Antennas.. 0 Viols.
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Sub-Area 1 complete. 95 Viols. 0
Warngs.
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Verification Complete. 95 Viols.
0 Warngs.

Could someone help me? I create the TLF file using syn2tlf. The TLF can be
imported into Cadence.

Thanks in advance.
Regards.
ykjing
 
I verified the libraries and found flowing errors:
** VERIFY-USER-24 PROBLEM **
VERIFY LIBRARY completed; errors (and warnings) found.
** CADENCE-USER-53 WARNING **
Input source will abort at next read due to limit of 1 PROBLEMs.
Message names are VERIFY-USER-n, from [n] in summary message.
1 Problem(s) [33]: adjacent routing layers without default via.
6 Problem(s) [134]: unreasonable via width.
7 total infos created.

Maybe it is the library causes the geometry viols.

Best Regards.
ykjing
"ykjing" <jhealthy@yeah.net> Đ´ČëĎűϢĐÂÎĹ:fqb9u3$efj$1@news.cn99.com...
Hi,
In Cadence SE, after floorplanning and add power ring, I verified
geometry. There is no viols. However ,after adding power strip, there are
four Antennas Viols.

I removed the power strips and placed cells with timing driven option,
there are lots of geometry viols as flows:

16:02:15 * VERIFY GEOMETRY CPU 0 0:00:00 Sub-Area 1 of 1.. 0 Viols.
16:02:15 * VERIFY GEOMETRY CPU 0 0:00:00 Cells.. 82
Viols.
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Special Wiring.. 13 Viols
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Regular Wiring.. 0 Viols
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Same-Net.. 0 Viols.
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Same-Net.. 0 Viols.
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Antennas.. 0 Viols.
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Sub-Area 1 complete. 95 Viols. 0
Warngs.
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Verification Complete. 95
Viols. 0 Warngs.

Could someone help me? I create the TLF file using syn2tlf. The TLF can be
imported into Cadence.

Thanks in advance.
Regards.
ykjing
Click to expand...
 
Hi,
Could someone help with the problem:

'Message names are VERIFY-USER-n, from [n] in summary message.
: adjacent routing layers without default via.
6 Problem(s) [134]: unreasonable via width.
'
Click to expand...
Thank you very much in advance.
Regards.
ykjing

"ykjing" <jhealthy@yeah.net> Đ´ČëĎűϢĐÂÎĹ:fqbfql$m7e$1@news.cn99.com...
I verified the libraries and found flowing errors:
** VERIFY-USER-24 PROBLEM **
VERIFY LIBRARY completed; errors (and warnings) found.
** CADENCE-USER-53 WARNING **
Input source will abort at next read due to limit of 1 PROBLEMs.
Message names are VERIFY-USER-n, from [n] in summary message.
1 Problem(s) [33]: adjacent routing layers without default via.
6 Problem(s) [134]: unreasonable via width.
7 total infos created.

Maybe it is the library causes the geometry viols.

Best Regards.
ykjing
"ykjing" <jhealthy@yeah.net> Đ´ČëĎűϢĐÂÎĹ:fqb9u3$efj$1@news.cn99.com...
Hi,
In Cadence SE, after floorplanning and add power ring, I verified
geometry. There is no viols. However ,after adding power strip, there are
four Antennas Viols.

I removed the power strips and placed cells with timing driven option,
there are lots of geometry viols as flows:

16:02:15 * VERIFY GEOMETRY CPU 0 0:00:00 Sub-Area 1 of 1.. 0 Viols.
16:02:15 * VERIFY GEOMETRY CPU 0 0:00:00 Cells.. 82
Viols.
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Special Wiring.. 13
Viols
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Regular Wiring.. 0 Viols
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Same-Net.. 0
Viols.
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Same-Net.. 0
Viols.
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Antennas.. 0
Viols.
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Sub-Area 1 complete. 95 Viols.
0 Warngs.
16:02:16 * VERIFY GEOMETRY CPU 0 0:00:00 Verification Complete. 95
Viols. 0 Warngs.

Could someone help me? I create the TLF file using syn2tlf. The TLF can
be imported into Cadence.

Thanks in advance.
Regards.
ykjing
Click to expand...
 
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