How to clarify algorithm of hardware(HDL)?

[Davy]

Hi all,

I am a new hardware algorithm engineer(deal with communication
algorithm and HDL implementation).
And I used to draw hardware diagram and timing chart to represent a
algorithm of hardware.
But I found it is a hard job to clarify algorithm of hardware by above
technique.

But I read a book by Ciletti "Advanced Digital Design with the Verilog
HDL". The book deal it
with algorithmic state machine-datapath (ASMD) chart. Is it useful?

Or can you give me some reference?

Any suggestions will be appreciated!
Best regards,
Davy

 

[Mike Treseler]

Davy wrote:

I used to draw hardware diagram and timing chart to represent a
algorithm of hardware.
But I found it is a hard job to clarify algorithm of hardware by above
technique.

I agree. I use a simulation testbench review.

But I read a book by Ciletti "Advanced Digital Design with the Verilog
HDL". The book deal it
with algorithmic state machine-datapath (ASMD) chart. Is it useful?

Not for design verification.
A manual chart could only cover a textbook example.

-- Mike Treseler

 

[Keith]

On Sat, 15 Apr 2006 20:56:35 -0700, Davy wrote:

Hi all,

I am a new hardware algorithm engineer(deal with communication
algorithm and HDL implementation).
And I used to draw hardware diagram and timing chart to represent a
algorithm of hardware.
But I found it is a hard job to clarify algorithm of hardware by above
technique.

I draw state diagrams if they're not too complicated. A state
transition table works for more complicated designs (though my VHDL reads
pretty much like a transition table).

But I read a book by Ciletti "Advanced Digital Design with the Verilog
HDL". The book deal it
with algorithmic state machine-datapath (ASMD) chart. Is it useful?

Haven't read the book.

Or can you give me some reference?

--
Keith