How to chnge this VHDL code into Verilog code

[Haimanot Tizazu]

architecture structural of prince_core is
type round_constants is array(0 to 11) of std_logic_vector(63 downto 0);
type intermediate_signals is array(0 to 11) of std_logic_vector(63 downto 0);

-- Round constants for each round
constant rcs: round_constants := (x"0000000000000000",
x"13198A2E03707344",
x"A4093822299F31D0",
x"082EFA98EC4E6C89",
x"452821E638D01377",
x"BE5466CF34E90C6C",
x"7EF84F78FD955CB1",
x"85840851F1AC43AA",
x"C882D32F25323C54",
x"64A51195E0E3610D",
x"D3B5A399CA0C2399",
x"C0AC29B7C97C50DD");

-- Signals for transporting the data between rounds
signal ims: intermediate_signals;
signal middle1, middle2: std_logic_vector(63 downto 0);

 

[gtwrek]

In article <48c017ed-9e97-4ff3-94eb-2fd4e39f5524@googlegroups.com>,
Haimanot Tizazu <htizazu@gmail.com> wrote:

architecture structural of prince_core is
type round_constants is array(0 to 11) of std_logic_vector(63 downto 0);
type intermediate_signals is array(0 to 11) of std_logic_vector(63 downto 0);

-- Round constants for each round
constant rcs: round_constants := (x"0000000000000000",
x"13198A2E03707344",
x"A4093822299F31D0",
x"082EFA98EC4E6C89",
x"452821E638D01377",
x"BE5466CF34E90C6C",
x"7EF84F78FD955CB1",
x"85840851F1AC43AA",
x"C882D32F25323C54",
x"64A51195E0E3610D",
x"D3B5A399CA0C2399",
x"C0AC29B7C97C50DD");

-- Signals for transporting the data between rounds
signal ims: intermediate_signals;
signal middle1, middle2: std_logic_vector(63 downto 0);

How's this for a start?

typedef bit [ 0 : 11 ] [ 63 : 0 ] round_constants;
typedef bit [ 0 : 11 ] [ 63 : 0 ] intermediate_signals;
round_constants rcs = {
'h0,
'h13198A2E03707344,
....
};
// Verilog has a "const" tag too, however, I never use it - can't
// see the point of using it.

intermediate_signals ims;
bit [ 63 : 0 ] middle1. middle2;

Regards,

Mark