How to change "X" to "0" or "1" (VHDL) ?

[Vakaras]

Hello,

I wroted a simple process to synchronyze Dat signal with a clock,
and when a "Dat" pulse edge is very close to "Clock", timing
simulation shows "X". And a simulation of the rest signals fails. How
to solve it?

My text is:

A0: process(Clock)
begin
if Clock'event and Clock='0' then
Dat2 <= Dat;
end if;
end process A0;

Result of timing diagram (Aldec 5.2) I put at:

http://www.electronicsdesigns.net/img/timings.gif

Thank you in advance for any suggestion.

 

[Vinh Pham]

Your problem could be the fact that your sensitivity list is incomplete.
Replace this:

A0: process(Clock)

With:

A0: process(Clock,Dat)

An incomplete sensitivity list can cause strange simulation results in
Aldec. You would think Aldec would give you a warning when your sensitivity
list is incomplete. So what I end up doing is enter my design in Aldec.
Synthesize the design in Synplicity, which does give you a warning. Fix the
sensitivity lists. THEN simulate it in Aldec.

Perhaps there is a way to make Aldec give you a warning or maybe the latest
version of Aldec does it.

Well hopefully that fixes your problem. I can't see any other reason for
the 'X'.


Regards,
Vinh

 

[Simon Peacock]

congratulations.. I think you have simulated metastability
dat doesn't need to be in your sensitivity list as dat changing won't affect
the simulation result unless clk changes.

What you are seeing is a setup time violation.
What you need to do is to sample data only when its valid, or if data is
truly asynchronous to clk, chain 2 or 3 flip flops to form a shift register.
This doesn't cure the problem, but will stop it occurring most of the time.

Then go and search the web and this news group for metastability issues.

Simon


"Vakaras" <dainius@electronicsdesigns.net> wrote in message
news:1682a848.0309252247.6374df38@posting.google.com...

Hello,

I wroted a simple process to synchronyze Dat signal with a clock,
and when a "Dat" pulse edge is very close to "Clock", timing
simulation shows "X". And a simulation of the rest signals fails. How
to solve it?

My text is:

A0: process(Clock)
begin
if Clock'event and Clock='0' then
Dat2 <= Dat;
end if;
end process A0;

Result of timing diagram (Aldec 5.2) I put at:

http://www.electronicsdesigns.net/img/timings.gif

Thank you in advance for any suggestion.

 

[Vinh Pham]

congratulations.. I think you have simulated metastability
dat doesn't need to be in your sensitivity list as dat changing won't
affect
the simulation result unless clk changes.

What you are seeing is a setup time violation.

Simon, I think if you carefully look at the timing diagram, it's clearly a
hold-time violation. And what an awful flip-flop, to have such a long
meta-stability resolution time. Perhaps an upgrade to Aldec 6.1 will
provide better performing flip-flop models.

Just joking, of course :_)


Regards,
Vinh

 

[Vakaras]

Hello,

Thanks for everybody.
Seems, that Flip-flops would be the best solution.
Yes, Aldec gave me a warning, but ... nothing to do with it..

Becouse "X" will be "0" or "1" in real, so I simply shifted testable
"Dat" signal, adjusted a freequency to be repeated of Clock, and it
worked.

Other partitial solution of this problem - to make "And" operation
with "X" and the same "Dat" signal after a short delay: "X and 0 = 0".
But it will work only with negative "Dat" edge. For positive, "X or 1
= 1", will work too. But no chanse to find a way, how to force to work
for both edges...

/Vakaras/

 

[Andy Peters]

"Vinh Pham" <a@a.a> wrote in message news:<zBRcb.15408$5z.9033@twister.socal.rr.com>...

Your problem could be the fact that your sensitivity list is incomplete.
Replace this:

A0: process(Clock)

With:

A0: process(Clock,Dat)

An incomplete sensitivity list can cause strange simulation results in
Aldec. You would think Aldec would give you a warning when your sensitivity
list is incomplete.

It may not be incomplete; see below.

So what I end up doing is enter my design in Aldec.
Synthesize the design in Synplicity, which does give you a warning. Fix the
sensitivity lists. THEN simulate it in Aldec.

Um, this is wrong -- if he's trying to build a flip-flop, the ONLY
signals that should be in the sensitivity list are the clock and
perhaps an async set/reset. Remember that a clocked flop's output
doesn't change when the input changes!

--a

 

[Simon Peacock]

I stand corrected.. but as with metastability.. you always get a 50/50
chance of being right
but I believe setup or hold both give the same problem.

Simon

"Vinh Pham" <a@a.a> wrote in message
news:SpScb.15906$5z.8325@twister.socal.rr.com...

congratulations.. I think you have simulated metastability
dat doesn't need to be in your sensitivity list as dat changing won't
affect
the simulation result unless clk changes.

What you are seeing is a setup time violation.

Simon, I think if you carefully look at the timing diagram, it's clearly a
hold-time violation. And what an awful flip-flop, to have such a long
meta-stability resolution time. Perhaps an upgrade to Aldec 6.1 will
provide better performing flip-flop models.

Just joking, of course :_)


Regards,
Vinh

 

[Vinh Pham]

I stand corrected.. but as with metastability.. you always get a 50/50
chance of being right

Heh I had no clue which it was.

but I believe setup or hold both give the same problem.

I'm no expert, but that sounds reasonable. In the end, it's still A Bad
Thing (tm).


--Vinh

 

[rickman]

Actually setup and hold times are to prevent metastabiltity. In this
case it is most likely that the OP does not care if the output reflects
the changed input or not. So either a 1 or a 0 would do fine. But
metastability has the potential of spreading through a circuit and
causing erroneous operation.

The problem here is that the OP does not understand the issue of
metastability. It is not clear to me if he had really fixed anything by
changing his simulation or if he is just covering up a potential problem
in his design.

To the best of my knowledge, there is no good simulation of
metastability and it can be hard to simulate a circuit that "fixes"
metastability since it only sees that the setup and hold were violated
and does not understand that the "fix" will solve the problem with a
very low failure rate. So the OP may be doing the right thing to get
the simulation to work as long as he understands the metastability
issue.


Simon Peacock wrote:

I stand corrected.. but as with metastability.. you always get a 50/50
chance of being right
but I believe setup or hold both give the same problem.

Simon

"Vinh Pham" <a@a.a> wrote in message
news:SpScb.15906$5z.8325@twister.socal.rr.com...
congratulations.. I think you have simulated metastability
dat doesn't need to be in your sensitivity list as dat changing won't
affect
the simulation result unless clk changes.

What you are seeing is a setup time violation.

Simon, I think if you carefully look at the timing diagram, it's clearly a
hold-time violation. And what an awful flip-flop, to have such a long
meta-stability resolution time. Perhaps an upgrade to Aldec 6.1 will
provide better performing flip-flop models.

Just joking, of course :_)


Regards,
Vinh

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

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