How to chang the clock tree structure in SE?

[dragon]

Hi,

Now I am dedicating in gating clock in a VLSI project. I want to

insert low power clock tree in silicon ensemble. It should be low power

by inserting as many as clock buffers after gated cell. But SE insert all

buffers before gated cell, so there's higher power dissipation in clock

tree.

I learned that there's some methods to change the clock buffer structure

to move the buffers after gated cell. But I don't know how to do that? Can

anyone give me some tips?


Best Regards
Yang Jun

 

[Parikshit Kumar]

Hi,
I assume you are using ctgen to generate clock tree, if tha's right then you
can try
specify_tree
root_pin 'name of the cellwhere you perform gating' 'output pin name
of the cell'
leaf_pins 'if there are any non-clock targets'
set_constraints
define_cells

the important point here is to use "root_pin" and not root "root_iopin".

good luck
Parikshit

"dragon" <draggonyang@gazeta.pl> wrote in message
news:bg2076$j1i$1@inews.gazeta.pl...

Hi,

Now I am dedicating in gating clock in a VLSI project. I want to

insert low power clock tree in silicon ensemble. It should be low power

by inserting as many as clock buffers after gated cell. But SE insert all

buffers before gated cell, so there's higher power dissipation in clock

tree.

I learned that there's some methods to change the clock buffer
structure

to move the buffers after gated cell. But I don't know how to do that? Can

anyone give me some tips?


Best Regards
Yang Jun