How to call verilog file as a PACKAGE in VHDL.

[dipesh.trivedi]

Dear Friends,

I am doing conversion of VHDL to Verilog of some of my project files.
Using tool called VISUAL ELITE.
But its not supporting CONSTANT's of VHDL. So not able to do it. So i
have converted that package file into verilog by changing CONSTANT
with PARAMETER of verilog. Now i have to call this file in VHDL.
Is it possible to call this file and use it as a PACKAGE???

Please Guide me...
Thanks in advance...
Waitin for ur replies...

 

[Evan Lavelle]

On Mon, 09 Jul 2007 02:53:14 -0000, "dipesh.trivedi"
<dipesh.trivedi@gmail.com> wrote:

Dear Friends,

I am doing conversion of VHDL to Verilog of some of my project files.
Using tool called VISUAL ELITE.
But its not supporting CONSTANT's of VHDL. So not able to do it. So i
have converted that package file into verilog by changing CONSTANT
with PARAMETER of verilog. Now i have to call this file in VHDL.
Is it possible to call this file and use it as a PACKAGE???

Your question doesn't really make sense. Why would you want to convert
a VHDL package into Verilog, and then "call" that Verilog "package"
from VHDL? You need to be more specific about exactly what your
problem is.

Some simulators will allow mixed-language simulation; you need to
check your simulator docs. Generally, you'll be able to instantiate a
Verilog module into a VHDL architecture, or a VHDL
configuration/component into a Verilog module. If you need to convert
a package, then you'll probably have to manually translate whatever
its contents are, and `include the result in a Verilog module.

Waitin for ur replies...

Ur is, or was, a Sumerian city. If you're waiting for a reply from it,
then you're out of luck. If, on the other hand, you're trying to spell
the possessive pronoun in English, you should perhaps stick with
"your".

Evan

 

[Niv]

On 9 Jul, 10:17, Evan Lavelle <nos...@nospam.com> wrote:

On Mon, 09 Jul 2007 02:53:14 -0000, "dipesh.trivedi"

dipesh.triv...@gmail.com> wrote:
Dear Friends,

I am doing conversion of VHDL to Verilog of some of my project files.
Using tool called VISUAL ELITE.
But its not supporting CONSTANT's of VHDL. So not able to do it. So i
have converted that package file into verilog by changing CONSTANT
with PARAMETER of verilog. Now i have to call this file in VHDL.
Is it possible to call this file and use it as a PACKAGE???

Your question doesn't really make sense. Why would you want to convert
a VHDL package into Verilog, and then "call" that Verilog "package"
from VHDL? You need to be more specific about exactly what your
problem is.

Some simulators will allow mixed-language simulation; you need to
check your simulator docs. Generally, you'll be able to instantiate a
Verilog module into a VHDL architecture, or a VHDL
configuration/component into a Verilog module. If you need to convert
a package, then you'll probably have to manually translate whatever
its contents are, and `include the result in a Verilog module.

Waitin for ur replies...

Ur is, or was, a Sumerian city. If you're waiting for a reply from it,
then you're out of luck. If, on the other hand, you're trying to spell
the possessive pronoun in English, you should perhaps stick with
"your".

Evan

I really want to see what the leading HDL citezen(s) of Ur have to
say!
Perhaps they have a Rosetta Stone equivalent for VHDL to Verilog.