How to build this MUX with sel=x?...

[Mike Lyu]

If I want when two-input mux sel is \"x\" but still want to output D0, intead of \"x\", how should I build the mux in verilog? This is for both simulation and synthesis.

The truth table will be:
Output
S=0 D0
S=x D0
S=1 D1

 

[Kevin Neilson]

On Tuesday, August 3, 2021 at 1:24:07 PM UTC-6, Mike Lyu wrote:

If I want when two-input mux sel is \"x\" but still want to output D0, intead of \"x\", how should I build the mux in verilog? This is for both simulation and synthesis.

The truth table will be:
Output
S=0 D0
S=x D0
S=1 D1

You can probably do this with \"casex\". You might also be able to use ===, as in:

assign dout = S===\'1b1 ? D1 : D0; // If S===1\'bx, output should(?) be D0

 

[Richard Damon]

On 8/3/21 3:24 PM, Mike Lyu wrote:

If I want when two-input mux sel is \"x\" but still want to output D0, intead of \"x\", how should I build the mux in verilog? This is for both simulation and synthesis.

The truth table will be:
Output
S=0 D0
S=x D0
S=1 D1

I would think carefully if that is really what you want to do and its
implications, such design can\'t really be implemented.

Remember, REAL hardware doesn\'t have a \'x\' state, a bit will be 0, or 1,
or perhaps Z if you are at a point which can be put into high impedance.

X represents a condition where we don\'t really know the state of the signal.

You could perhaps add logic so that if D0 and D1 are the same, then if
S=x you output that value, but forcing the output to be D0 when S=x will
make the simulation \'inaccurate\' if you really want to see what would
happen in this case in actual hardware.