How to build a VHDL package in order to use it in other proj

[Victor-Bossennec]

Hi everybody,

I use a Lattice LFXP6C FPGA with Lattice Diamond EDI and Synplify Pr
synthesizer, and I have to design several projects dealings with variou
elementary VHDL blocs like Clock divider, Counter, Edge detector, FIFO...
So I'm trying to develop my own package which is defining all of thos
components. Therefore I have created a project with all the blocs' sourc
code and the package source code.

But when I try to synthesize this project, it seems that only one of th
entity is synthesized by SynplifyPro.

Here is two examples of my bloc's source code :
* Clock divider :
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity slib_clock_div is
generic (
RATIO : integer := 4 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end slib_clock_div;

architecture rtl of slib_clock_div is
-- Signals
signal iQ : std_logic; -- Internal Q
signal iCounter : integer range 0 to RATIO-1; -- Counter

begin
-- Main process
CD_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= 0;
iQ <= '0';
elsif (CLK'event and CLK='1') then
iQ <= '0';
if (CE = '1') then
if (iCounter = (RATIO-1)) then
iQ <= '1';
iCounter <= 0;
else
iCounter <= iCounter + 1;
end if;
end if;
end if;
end process;

-- Output signals
Q <= iQ;
end rtl;



* Counter :
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- Counter
entity slib_counter is
generic (
WIDTH : natural := 4 -- Counter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear counter register
LOAD : in std_logic; -- Load counter register
ENABLE : in std_logic; -- Enable count operation
DOWN : in std_logic; -- Count direction down
D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input
Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output
OVERFLOW : out std_logic -- Counter overflow
);
end slib_counter;

architecture rtl of slib_counter is
signal iCounter : unsigned(WIDTH downto 0); -- Counter register
begin
-- Counter process
COUNT_SHIFT: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= (others => '0'); -- Reset counter register
elsif (CLK'event and CLK='1') then
if (CLEAR = '1') then
iCounter <= (others => '0'); -- Clear counter register
elsif (LOAD = '1') then -- Load counter register
iCounter <= unsigned('0' & D);
elsif (ENABLE = '1') then -- Enable counter
if (DOWN = '0') then -- Count up
iCounter <= iCounter + 1;
else -- Count down
iCounter <= iCounter - 1;
end if;
end if;
if (iCounter(WIDTH) = '1') then -- Clear overflow
iCounter(WIDTH) <= '0';
end if;
end if;
end process;

-- Output ports
Q <= std_logic_vector(iCounter(WIDTH-1 downto 0));
OVERFLOW <= iCounter(WIDTH);
end rtl;



* Package :
library ieee;
use ieee.std_logic_1164.all;

use work.all;

package stdlib is
----------------------------------------------------------------------
-- Component declarations
----------------------------------------------------------------------
component SLIB_CLOCK_DIV is
generic (
RATIO : integer := 4 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end component SLIB_CLOCK_DIV;

component SLIB_COUNTER is
generic (
WIDTH : natural := 4 -- Counter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear counter register
LOAD : in std_logic; -- Load counter register
ENABLE : in std_logic; -- Enable count operation
DOWN : in std_logic; -- Count direction down
D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input
Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output
OVERFLOW : out std_logic -- Counter overflow
);
end component SLIB_COUNTER;
end package stdlib;



* Synplify report :
************************************************************
** Synplify Pro **
************************************************************
synpwrap -prj "Std_Package_Standard_synplify.tcl" -log
"Std_Package_Standard.srf"
Copyright (C) 1992-2010 Lattice Semiconductor Corporation. All rights
reserved.
Lattice Diamond Version 1.1.01.50.42.10

==contents of Std_Package_Standard.srf
#Build: Synplify Pro for Lattice D-2010.03L-SP1, Build 142R, Aug 11 2010
#install: C:\lscc\diamond\1.1\synpbase
#OS: Windows_NT

#Hostname: XXXXXX

$ Start of Compile
#Wed Feb 23 10:50:54 2011

Synopsys VHDL Compiler, version comp510rc, Build 126R, built Jul 22 2010
@N|Running in 32-bit mode
Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved

@N: CD720
:"C:\lscc\diamond\1.1\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time
resolution to ns
@N:"C:\...\Standard\source\slib_counter.vhd":28:7:28:21|Top entity is set
to slib_counter.
VHDL syntax check successful!
@N: CD630
:"C:\...\Standard\source\slib_counter.vhd":28:7:28:21|Synthesizing
work.slib_counter.rtl
Post processing for work.slib_counter.rtl
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Feb 23 10:50:54 2011



Another issue is that I can't use the package in another project.
This second project has only the package source code (and it's own source
which use some elementary blocs). The check syntax and synthesize is ok,
but all the components from my package are replaced by a BlackBox and the
process abords with errors when translating the design.

* Here is the source code :
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.stdlib.all;

-- Serial UART
entity uart is
port (
...
);
end uart;

architecture rtl of uart is
...
-- Clock enable generation
component SLIB_CLOCK_DIV is
generic (
RATIO : integer := 8 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end component;
...
begin
...
UART_BG2: slib_clock_div generic map (RATIO => 8)
port map (
CLK => CLK,
RST => RST,
CE => iBaudtick16x,
Q => iBaudtick2x
);
...
end rtl;



*The warning/error I get :
...
@W: CD280 :"C:\...\UART\source\uart.vhd":208:14:208:27|Unbound component
SLIB_CLOCK_DIV mapped to black box
...
ERROR - ngdbuild: logical block 'UART_BG2' with type 'SLIB_CLOCK_DIV' is
unexpanded



So it seems that I'm doing it the wrong way !
I've made some research and it appears that I should create a VHDL Library,
but I didn't find any useful tutorial to describre this.

Can somebody explain me where are my mistakes ?

Why am I not able to synthesize all the entities of my package's project as
they are independants ? Is it possible to synthesize without a Top ?

What should I do in order to be able to compile my elementary blocs and
then easily reuse it in another projects ?

Thanks for your help !

Regards,
Victor.



---------------------------------------
Posted through http://www.FPGARelated.com

 

[RCIngham]

[Original post elided]

I suspect that you are confusing libraries and packages. A package ca
contain component declarations relating to multiple entities, bu it doe
not contain those entities and the corresponding architectures.

Also, some synthesis tools - but perhaps not yours - are not very cleve
regarding multiple user-defined libraries (that is, other than 'work').
suggest that you look in the tool documentation for a tutorial entitle
something like "Working with libraries".

You can share pre-compiled libraries between projects, but it may not b
simple to do.


---------------------------------------
Posted through http://www.FPGARelated.com

 

[Victor-Bossennec]

Hi RCIngham,

I may be a bit confused as I'm a newbie in the FPGA world...

So as I've found, I should set up a library. But I don't know how to d
it.
I didn't find any documentation about creating libraries and the Synplif
Pro User Guide is not helpful on that topic ! I will try to find that kin
of guide.

Thanks for your answer.

I suspect that you are confusing libraries and packages. A package can
contain component declarations relating to multiple entities, bu it does
not contain those entities and the corresponding architectures.

Also, some synthesis tools - but perhaps not yours - are not very clever
regarding multiple user-defined libraries (that is, other than 'work'). I
suggest that you look in the tool documentation for a tutorial entitled
something like "Working with libraries".

You can share pre-compiled libraries between projects, but it may not be
simple to do.


---------------------------------------
Posted through http://www.FPGARelated.com

---------------------------------------
Posted through http://www.FPGARelated.com