How to bring PLL's output to Pin_F1

[enq_semi]

Hi,

Here is my question:

Device: APEX EP20K1500

I use the on-chip PLL to convert 40MHz Xtal clock to 56MHz clock and
want to watch this signal on oscilloscope.

Can I bring the PLL's output directly to Pin_F1 of JP10 or indirectly
to Pin_F1?

I know I can bring the PLL's output to "clock output pin" (i.e. U31 or
Y3), but, can I bring it to non-clock output pins?

Thank you very much for your help!

Yi Zhang
ENQ Semi.

 

[Hal Murray]

I know I can bring the PLL's output to "clock output pin" (i.e. U31 or
Y3), but, can I bring it to non-clock output pins?

I'm not familiar with the internals of the APEX EP20K1500.

If it was a Xilinx chip, I would use the normal special clock
distribution resources to route the clock to a FF next to
the output pin, toggle that FF, and then connect that FF
to the output pin.

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[Marc Randolph]

enq_semi wrote:

Device: APEX EP20K1500

I use the on-chip PLL to convert 40MHz Xtal clock to 56MHz clock and
want to watch this signal on oscilloscope.

Can I bring the PLL's output directly to Pin_F1 of JP10 or indirectly
to Pin_F1?

I know I can bring the PLL's output to "clock output pin" (i.e. U31 or
Y3), but, can I bring it to non-clock output pins?

Directly? I believe the answer is no. For all the excellent global
resources (better than Virtex II in some way) of the Apex 20K family,
this is one thing they appear to have left off (on purpose or accident,
I don't know).

And I recall it being painful to interface to the few clock outputs they
do provide (I think they provided a very small choice of driver types).

If you can use a second PLL to produce a 2x (112 MHz) clock, then
perhaps you could use the FF in the I/O cell to create the 56 MHz to
send off chip.

Marc