How to bind multiple sva modules(spec) with one verilog modu

S

samuel

Guest
Hi,

I have a verilog module (dut) composed of several different bus
interfaces , and I have the corresponding bus sva vip module for each
bus i/f. So I need bind them to the verilog module.

Does anyone know how to bind ?


Thanks in advance,

Samuel
 
On Jun 21, 8:14 am, samuel <samuelz...@gmail.com> wrote:
Hi,

I have a verilog module (dut) composed of several different bus
interfaces , and I have the corresponding bus sva vip module for each
bus i/f. So I need bind them to the verilog module.

Does anyone know how to bind ?

Thanks in advance,

Samuel
Click to expand...
try
bind <name of the module in which to bind>: <name of the instances in
which the to bind> <name of the module to be instantiated or bound>
<name of the instantation>( port map )

like

bind parag: p1,p2,p3 samuel s1(a,b,c);


where p1,p2 and p3 will have a mod instance s1 bound with a,b,c all
inside parag
-Parag
 
On Jun 21, 3:24 pm, "parag_p...@hotmail.com" <parag_p...@hotmail.com>
wrote:
On Jun 21, 8:14 am, samuel <samuelz...@gmail.com> wrote:

Hi,

I have a verilog module (dut) composed of several different bus
interfaces , and I have the corresponding bus sva vip module for each
bus i/f. So I need bind them to the verilog module.

Does anyone know how to bind ?

Thanks in advance,

Samuel

try
bind <name of the module in which to bind>: <name of the instances in
which the to bind> <name of the module to be instantiated or bound
name of the instantation>( port map )

like

bind parag: p1,p2,p3 samuel s1(a,b,c);

where p1,p2 and p3 will have a mod instance s1 bound with a,b,c all
inside parag
-Parag
Click to expand...

So here p1,p2,p3 is the vip module and samuel is the dut module ?

Rgds,

S.
 
On Jun 21, 3:24 pm, "parag_p...@hotmail.com" <parag_p...@hotmail.com>
wrote:
On Jun 21, 8:14 am, samuel <samuelz...@gmail.com> wrote:

Hi,

I have a verilog module (dut) composed of several different bus
interfaces , and I have the corresponding bus sva vip module for each
bus i/f. So I need bind them to the verilog module.

Does anyone know how to bind ?

Thanks in advance,

Samuel

try
bind <name of the module in which to bind>: <name of the instances in
which the to bind> <name of the module to be instantiated or bound
name of the instantation>( port map )

like

bind parag: p1,p2,p3 samuel s1(a,b,c);

where p1,p2 and p3 will have a mod instance s1 bound with a,b,c all
inside parag
-Parag
Click to expand...
So p1,p2,p3 are sva vips and samuel is the verilog dut module ,
right ?

Rgds,

S.
 
On Jun 22, 8:48 am, samuel <samuelz...@gmail.com> wrote:
On Jun 21, 3:24 pm, "parag_p...@hotmail.com" <parag_p...@hotmail.com
wrote:



On Jun 21, 8:14 am, samuel <samuelz...@gmail.com> wrote:

Hi,

I have a verilog module (dut) composed of several different bus
interfaces , and I have the corresponding bus sva vip module for each
bus i/f. So I need bind them to the verilog module.

Does anyone know how to bind ?

Thanks in advance,

Samuel

try
bind <name of the module in which to bind>: <name of the instances in
which the to bind> <name of the module to be instantiated or bound
name of the instantation>( port map )

like

bind parag: p1,p2,p3 samuel s1(a,b,c);

where p1,p2 and p3 will have a mod instance s1 bound with a,b,c all
inside parag
-Parag

So here p1,p2,p3 is the vip module and samuel is the dut module ?

Rgds,

S.
Click to expand...
hi Samuel,
Yes ,
YOu will see the following hierarchial names after that
p1.s1
p2.s1
p3.s1

I hope this time I hit the gong
 
On Jun 22, 1:12 pm, "parag_p...@hotmail.com" <parag_p...@hotmail.com>
wrote:
On Jun 22, 8:48 am, samuel <samuelz...@gmail.com> wrote:



On Jun 21, 3:24 pm, "parag_p...@hotmail.com" <parag_p...@hotmail.com
wrote:

On Jun 21, 8:14 am, samuel <samuelz...@gmail.com> wrote:

Hi,

I have a verilog module (dut) composed of several different bus
interfaces , and I have the corresponding bus sva vip module for each
bus i/f. So I need bind them to the verilog module.

Does anyone know how to bind ?

Thanks in advance,

Samuel

try
bind <name of the module in which to bind>: <name of the instances in
which the to bind> <name of the module to be instantiated or bound
name of the instantation>( port map )

like

bind parag: p1,p2,p3 samuel s1(a,b,c);

where p1,p2 and p3 will have a mod instance s1 bound with a,b,c all
inside parag
-Parag

So here p1,p2,p3 is the vip module and samuel is the dut module ?

Rgds,

S.

hi Samuel,
Yes ,
YOu will see the following hierarchial names after that
p1.s1
p2.s1
p3.s1

I hope this time I hit the gong
Click to expand...
Thanks Parag,

But according to the systemverilog 3.1a spec , the module(dut) is
before the constraint/program (vip) when binding.
So ......

Rgds,

Samuel

The spec described below :

bind_directive ::= bind hierarchical_identifier constant_select
bind_instantiation ;
bind_instantiation ::=
program_instantiation
| module_instantiation
| interface_instantiation


Example of binding a program instance to a module:
bind cpu fpu_props fpu_rules_1(a,b,c);
Where:
- cpu is the name of module.
- fpu_props is the name of the program containing properties.
- fpu_rules_1 is the program instance name.
- Ports (a, b,c) get bound to signals (a,b,c) of module cpu.
- Every instance of cpu gets the properties.
Example of binding a program instance to a specific instance of a
module:
 
That simply means that the property will names

cpu.fpu_rules_1()
isnt it ?
We are both on the same boat but, you on star board and me on the port
side :)
-Parag


samuel wrote:
On Jun 22, 1:12 pm, "parag_p...@hotmail.com" <parag_p...@hotmail.com
wrote:
On Jun 22, 8:48 am, samuel <samuelz...@gmail.com> wrote:



On Jun 21, 3:24 pm, "parag_p...@hotmail.com" <parag_p...@hotmail.com
wrote:

On Jun 21, 8:14 am, samuel <samuelz...@gmail.com> wrote:

Hi,

I have a verilog module (dut) composed of several different bus
interfaces , and I have the corresponding bus sva vip module for each
bus i/f. So I need bind them to the verilog module.

Does anyone know how to bind ?

Thanks in advance,

Samuel

try
bind <name of the module in which to bind>: <name of the instances in
which the to bind> <name of the module to be instantiated or bound
name of the instantation>( port map )

like

bind parag: p1,p2,p3 samuel s1(a,b,c);

where p1,p2 and p3 will have a mod instance s1 bound with a,b,c all
inside parag
-Parag

So here p1,p2,p3 is the vip module and samuel is the dut module ?

Rgds,

S.

hi Samuel,
Yes ,
YOu will see the following hierarchial names after that
p1.s1
p2.s1
p3.s1

I hope this time I hit the gong

Thanks Parag,

But according to the systemverilog 3.1a spec , the module(dut) is
before the constraint/program (vip) when binding.
So ......

Rgds,

Samuel

The spec described below :

bind_directive ::= bind hierarchical_identifier constant_select
bind_instantiation ;
bind_instantiation ::=
program_instantiation
| module_instantiation
| interface_instantiation


Example of binding a program instance to a module:
bind cpu fpu_props fpu_rules_1(a,b,c);
Where:
- cpu is the name of module.
- fpu_props is the name of the program containing properties.
- fpu_rules_1 is the program instance name.
- Ports (a, b,c) get bound to signals (a,b,c) of module cpu.
- Every instance of cpu gets the properties.
Example of binding a program instance to a specific instance of a
module:
Click to expand...
 
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