How to avoid 'unable to synthesize' errors

[Anon Anon]

Can somebody recommend a book or on-line document that explains how to
avoid generating un-synthesizable code?

I recently wrote some VHDL code that looked fine to me and was close to
one of the Xilinx examples I'd seen, but it would not synthesize. I've
fixed that problem now (by a complete re-write) but I'd like to avoid
such problems in future and also get a clearer idea of what it is that
causes such issues.

Note that I am working in a Xilinx environment, using ISE 9.1.

Many thanks for any help!

AA

 

[Mike Treseler]

Anon Anon wrote:

Can somebody recommend a book or on-line document that explains how to
avoid generating un-synthesizable code?

Google this group.

Use a synchronous template.

No wizards/generators for simple stuff.

Verify functionality with vhdl simulation first.


-- Mike Treseler

 

[Ralf Hildebrandt]

Anon Anon schrieb:

Can somebody recommend a book or on-line document that explains how to
avoid generating un-synthesizable code?

You have 3 things that you can model with a HDL: combinational logic,
latches and flipflops:

process(a,b)
begin
if (a='1') then
logic<='0';
else logic<=b;
end if;
end process;

process(enable,data)
begin
if (enable='1') then
latch<=data;
end if;
end process;

process(async_reset,clock)
begin
if (async_reset='1') then
flipflop<='0';
elsif rising_edge(clock) then
flipflop<=data;
end if;
end process;

Three-state logic is something similar to combinational logic.

There are a lot of ways how to model these things. You can even put
everything into one process, as Mike Treseler suggests. I think for
beginners it is often more clear what will be the result if one uses
these templates.


Ralf