How to assign 'X' to a Systemverilog enum?

[news.la.sbcglobal.net]

I'm trying to simulate 'X' propogation through an enum-encoded
state-machine. But I can't seem to make this work. I've make sure the
typedef is based on a 4-state variable, but it won't initialize to 'X', nor
can I assign 'X' to it.

What am I doing wrong?

module foo;

typedef enum logic [3:0] { STATE_1=4'd0, STATE_2, STATE_3, STATE_4 }
t_statevector;

t_statevector present_state, next_state;

initial begin
// at time 0: simulator initializes present_state = STATE_1;

present_state = 'x; // COMPILE-ERROR!
end

endmodule

 

news.la.sbcglobal.net wrote:

I'm trying to simulate 'X' propogation through an enum-encoded
state-machine. But I can't seem to make this work. I've make sure the
typedef is based on a 4-state variable, but it won't initialize to 'X', nor
can I assign 'X' to it.

If a 4-state enum isn't initializing to X, then your simulator is not
compliant with the IEEE 1800 SystemVerilog standard, and you
should file a bug report with your simulator vendor. Some
simulators are still following the obsolete Accellera 3.1a LRM.

You should be able to assign X to it by using a static cast to the
enum type.

 

[wire signed [0:0]]

<sharp@cadence.com> wrote in message
news:1175113092.401026.126130@o5g2000hsb.googlegroups.com...

If a 4-state enum isn't initializing to X, then your simulator is not
compliant with the IEEE 1800 SystemVerilog standard, and you
should file a bug report with your simulator vendor. Some
simulators are still following the obsolete Accellera 3.1a LRM.

Is there a summary somewhere, explaining the differences between the
publically downloadable 3.1a LRM, and the offiicial IEEE 1800-2005 standard?

 

[wire signed [0:0]]

<sharp@cadence.com> wrote in message
news:1175113092.401026.126130@o5g2000hsb.googlegroups.com...

news.la.sbcglobal.net wrote:
I'm trying to simulate 'X' propogation through an enum-encoded
state-machine. But I can't seem to make this work. I've make sure the
typedef is based on a 4-state variable, but it won't initialize to 'X',
nor
can I assign 'X' to it.

If a 4-state enum isn't initializing to X, then your simulator is not
compliant with the IEEE 1800 SystemVerilog standard, and you
should file a bug report with your simulator vendor. Some
simulators are still following the obsolete Accellera 3.1a LRM.

I just tried this in Modelsim 6.2g PE Student Edition. That simulator
initializes 4-state enum's to the "leftmost" label -- definitely
non-compliant
behavior!

You should be able to assign X to it by using a static cast to the
enum type.

Yup, this worked! It's aggravating to have to use a static-cast,
instead of just directly assigning 'X to the variable.