How to assign an array to a vector?

[Peng Yu]

Hi,
The commended portion of the following code list isn't correct. If I
uncommend it, I'll get a error:
Error: assign.v(15): Range must be bounded by constant expressions
Although I can use the code segment
out[3:0] <= in[0];
out[7:4] <= in[1];
out[11:8] <= in[2];
out[15:12] <= in[3];
, I have to adjust the code if N != 4. Is there any solution to this
situation?
Thanks,
Peng


module assignment;
parameter N = 4;

reg [4 * N - 1:0] out;
reg [3:0] in[0:N - 1];
reg clock;

integer i;

always begin
@(posedge clock) begin
for(i = 0;i < N;i = i + 1)
in <= ~in;
/* for(i = 0;i < N;i = i + 1)
out[4 * i + 3:4 * i] <= in;
*/
out[3:0] <= in[0];
out[7:4] <= in[1];
out[11:8] <= in[2];
out[15:12] <= in[3];
end
end

initial begin
clock = 0; in[0] = 0; in[1] = 1; in[2] = 2; in[3] = 3;
$monitor("time=%0t,clock=%b,out=%h,in[0]=%h,in[1]=%h,in[2]=%h,in[3]=%h",
$time, clock, out, in[0], in[1], in[2], in[3]);
#100 $stop;
end

always
#10 clock = ~clock;

endmodule

 

[Jim Wu]

Verilog-1995 specifies the msb and lsb of a range have to be constants. The
following equation should work for you:

for(i = 0; i < N; i = i + 1)
out <= {in, out[15:4]};

Jim Wu
jimwu88NOOOOOSPAM@yahoo.com

Peng Yu <yupeng_@hotmail.com> wrote in message
news:d7b3726c.0308051833.4efe63e4@posting.google.com...

Hi,
The commended portion of the following code list isn't correct. If I
uncommend it, I'll get a error:
Error: assign.v(15): Range must be bounded by constant expressions
Although I can use the code segment
out[3:0] <= in[0];
out[7:4] <= in[1];
out[11:8] <= in[2];
out[15:12] <= in[3];
, I have to adjust the code if N != 4. Is there any solution to this
situation?
Thanks,
Peng


module assignment;
parameter N = 4;

reg [4 * N - 1:0] out;
reg [3:0] in[0:N - 1];
reg clock;

integer i;

always begin
@(posedge clock) begin
for(i = 0;i < N;i = i + 1)
in <= ~in;
/* for(i = 0;i < N;i = i + 1)
out[4 * i + 3:4 * i] <= in;
*/
out[3:0] <= in[0];
out[7:4] <= in[1];
out[11:8] <= in[2];
out[15:12] <= in[3];
end
end

initial begin
clock = 0; in[0] = 0; in[1] = 1; in[2] = 2; in[3] = 3;

$monitor("time=%0t,clock=%b,out=%h,in[0]=%h,in[1]=%h,in[2]=%h,in[3]=%h",
$time, clock, out, in[0], in[1], in[2], in[3]);
#100 $stop;
end

always
#10 clock = ~clock;

endmodule

 

[Steven Sharp]

yupeng_@hotmail.com (Peng Yu) wrote in message news:<d7b3726c.0308051833.4efe63e4@posting.google.com>...

Hi,
The commended portion of the following code list isn't correct. If I
uncommend it, I'll get a error:
Error: assign.v(15): Range must be bounded by constant expressions
, I have to adjust the code if N != 4. Is there any solution to this
situation?

Variables are illegal in part-selects, in order to guarantee that all
expressions have known constant widths at compile time. For situations
like yours, Verilog-2001 added the variable or indexed part select. If
your simulator supports that language feature, then you can do this.

/* for(i = 0;i < N;i = i + 1)
out[4 * i + 3:4 * i] <= in;
*/

// Solution using indexed part select
for (i = 0; i < N; i = i + 1)
out[4*i +: 4] = in;

The first value (before the + is a starting bit index, which can be
a variable expression. The second value (after the + is the width
of the part-select, which must be a constant expression. The use of
+: indicates that the other end of the range is in an upward direction
from the starting bit index, making it (start+(width-1)). There is
also a -: version of the indexed part-select, which causes the other
end of the range to be (start-(width-1)). This might look more
natural with your index direction because it would put the leftmost
end of the range as the left or starting index operand:

out[4*i+3 -: 4] = in;

If your tools don't support indexed part-selects, then the only
way to write parameterized code for this would be to add an inner
loop that assigns the bits one at a time, because variables are
allowed in bit-selects. However, then you would discover that
before Verilog-2001, you could not take a bit-select of a memory
(i.e. array) word. You would have to assign in to a vector
variable first, and then copy bits from that vector variable into
the appropriate bits of out.