How to add clock delay in CPLD?

[rat]

Hi,friends,
To meet the Tsu requirement in my design, I think I should try to add some
clock delay to the input register, how can I do that in CPLD? (not FPGA,
without PLL,DLL)

Thanks!

 

[Repzak]

"rat" <rattt@col.edu.cn> skrev i en meddelelse
news:cbnvnr$2od0$1@mail.cn99.com...

Hi,friends,
To meet the Tsu requirement in my design, I think I should try to add some
clock delay to the input register, how can I do that in CPLD? (not FPGA,
without PLL,DLL)

Hey

You could use a simple bianry counter....

bit 1 = IN
Bit 2 = In/2
Bit 3 = In/4
and so on...

Kasper

 

[Jim Granville]

rat wrote:

Hi,friends,
To meet the Tsu requirement in my design, I think I should try to add some
clock delay to the input register, how can I do that in CPLD? (not FPGA,
without PLL,DLL)

It depends on your signals.
Sometimes, you can use the opposite clock edge, to ensure stable
sampling points.
If that is too coarse, you can use delay passes, but they
need real care. Nodes can be removed/optimised away by tool flows,
or revisions in tool flows, and the delays are process dependant.
ie use only when all else fails.
-jg

 

[Uwe Bonnes]

Jim Granville <no.spam@designtools.co.nz> wrote:


: rat wrote:

: > Hi,friends,
: > To meet the Tsu requirement in my design, I think I should try to add some
: > clock delay to the input register, how can I do that in CPLD? (not FPGA,
: > without PLL,DLL)

: It depends on your signals.
: Sometimes, you can use the opposite clock edge, to ensure stable
: sampling points.
: If that is too coarse, you can use delay passes, but they
: need real care. Nodes can be removed/optimised away by tool flows,
: or revisions in tool flows, and the delays are process dependant.
: ie use only when all else fails.

Going off- and on-chip again gives also some delay that no optimizer will
optimize away, at the expense of two pins...

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[rat]

Going off- and on-chip again gives also some delay that no optimizer will
optimize away, at the expense of two pins...

Good idea But it seems that it is hard to do the simulation and timing
analysis

 

[Uwe Bonnes]

rat <rattt@col.edu.cn> wrote:


: > Going off- and on-chip again gives also some delay that no optimizer will
: > optimize away, at the expense of two pins...

: Good idea But it seems that it is hard to do the simulation and timing
: analysis

Put the delay, taken from the data sheet, into the test bench...

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Hal Murray]

Going off- and on-chip again gives also some delay that no optimizer will
optimize away, at the expense of two pins...

Suppose I go off and back on using a single pin. How much software
is "smart" enough to optimize that out?

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[John Adair]

Have a look at the differences between fabric clocks, sometimes called
asynchronous (but they are not), and global clocks. You usually get a timing
shift between these. Alternatively consider negative edge clocks or if you
are using Coolrunner2 the clock doubling features.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk

This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.

"rat" <rattt@col.edu.cn> wrote in message
news:cbnvnr$2od0$1@mail.cn99.com...

Hi,friends,
To meet the Tsu requirement in my design, I think I should try to add some
clock delay to the input register, how can I do that in CPLD? (not FPGA,
without PLL,DLL)

Thanks!

 

[pablo aimar]

Hi,
you can try following method:
take the clock input from clock oscillator to pin A of cpld, bring
it out through pin B and now give it to global clock(global lines)
pin, by this method you can have some delay (I/O buffer delay), but
you need to scarifice two pins of cpld.
----
Insert two inverters in the clock path, assign output of first inv
to a io pin,(not optimized out) use the o/p of second inverter. here
the clock is no longer assigned to global lines. for simple logic this
may work.

Thanks
rao

news:cbnvnr$2od0$1@mail.cn99.com...
Hi,friends,
To meet the Tsu requirement in my design, I think I should try to add some
clock delay to the input register, how can I do that in CPLD? (not FPGA,
without PLL,DLL)

Thanks!