How may I restrain the P&R to only a small area...

[Tungsten-W]

Hi, there:

I am doing a design which only covers 10% of the slices...but after P&R, it
spreaded all over the FPGA.
How may I constrain it into, say, one corner...

How may I "nail down the logic into a known location"(Somebody told me this
trick)?

BTW, I am doing reconfigurable design, so the AREA_GROUP constraints can't
be used...

Kelvin

 

[John_H]

"Tungsten-W" <kelvin8157@hotmail.com> wrote in message news:<40232edf$1@news.starhub.net.sg>...

Hi, there:

I am doing a design which only covers 10% of the slices...but after P&R, it
spreaded all over the FPGA.
How may I constrain it into, say, one corner...

How may I "nail down the logic into a known location"(Somebody told me this
trick)?

BTW, I am doing reconfigurable design, so the AREA_GROUP constraints can't
be used...

Kelvin

How about trying to constrain the design to NOT be placed in regions?
Check the CONFIG PROHIBIT constraint in the online constraints guide.
This could work for you.

 

[Chris Ebeling]

Xilinx Docs -> Constraint Guide -> AREA_GROUP
http://toolbox.xilinx.com/docsan/xilinx6/books/manuals.htm

Tungsten-W wrote:

Hi, there:

I am doing a design which only covers 10% of the slices...but after P&R, it
spreaded all over the FPGA.
How may I constrain it into, say, one corner...

How may I "nail down the logic into a known location"(Somebody told me this
trick)?

BTW, I am doing reconfigurable design, so the AREA_GROUP constraints can't
be used...

Kelvin

 

[Chris Ebeling]

Apologies,
I didn't read your post very carefully have you looked at this?
http://www.xilinx.com/bvdocs/appnotes/xapp290.pdf

Chris Ebeling wrote:

Xilinx Docs -> Constraint Guide -> AREA_GROUP
http://toolbox.xilinx.com/docsan/xilinx6/books/manuals.htm

Tungsten-W wrote:

Hi, there:

I am doing a design which only covers 10% of the slices...but after P&R, it
spreaded all over the FPGA.
How may I constrain it into, say, one corner...

How may I "nail down the logic into a known location"(Somebody told me this
trick)?

BTW, I am doing reconfigurable design, so the AREA_GROUP constraints can't
be used...

Kelvin

 

[Kelvin @ SG]

Thank you Chris.

I have read the xapp290...
However I have defined AREA_GROUP on each modules of my design, now I need
to restrain the P&R of a particular module to be within a corner of the
module's AREA_GROUP instead...

Best Regards,
Kelvin




"Chris Ebeling" <christopher.ebeling@xilinx.com> wrote in message
news:4027E24B.10145AF8@xilinx.com...

Apologies,
I didn't read your post very carefully have you looked at this?
http://www.xilinx.com/bvdocs/appnotes/xapp290.pdf

Chris Ebeling wrote:

Xilinx Docs -> Constraint Guide -> AREA_GROUP
http://toolbox.xilinx.com/docsan/xilinx6/books/manuals.htm

Tungsten-W wrote:

Hi, there:

I am doing a design which only covers 10% of the slices...but after
P&R, it
spreaded all over the FPGA.
How may I constrain it into, say, one corner...

How may I "nail down the logic into a known location"(Somebody told me
this
trick)?

BTW, I am doing reconfigurable design, so the AREA_GROUP constraints
can't
be used...

Kelvin