How many syntaxes in Spectre?

[Eric Lau]

A little bit confused about Spectre syntax. Besides the so-called
Spectre syntax, is MDL part of it? What about the syntax used in
Spectre format model card???
Please clarify. Thanks a million!
Eric

 

[Andrew Beckett]

Spectre understands a number of things (in no particular order, and by
no means a complete definition of each):

1. spectre syntax
This is the syntax used in spectre netlists to define instances, analyses,
models etc. Simplistically, it is of the form:

instanceName (conn1 conn2 conn3) blockName param1=val param2=val

The list of connections isn't needed for all components/analyses. The
blockName can be a builtin primitive, a model, a subckt, a verilog-a or
spectreHDL module. Note that analyses are also described this way.

Spectre also understands expressions - see "spectre -h expressions" for more
details, and parameter passing. There are a few other things in the
language, like:

parameters param1=default1 param2=default2

model modelName primitive param1=val1 param2=val2

So spectre models are also in "spectre syntax".

2. spice syntax

Spectre understands (natively) a limited set of SPICE syntax:

R1 A B r=1k
.tran 1n 100n

for example. Any file that doesn't have a ".scs" suffix is assumed to be in
spice syntax unless the directive:

simulator lang=spectre
or
simulator lang=spice

is used to override things.

Currently the spice syntax support is somewhat limited; this will be
improving (vastly) with the new front end coming in IC5141; up until that
point there is "spp" which is a spice-preprocessor which can convert SPICE
syntax (various dialects) into spectre's syntax as a preprocessing option.

3. Verilog-A

It is possible to write Verilog-A modules using the standard
http://www.accellera.com language. These are included into the netlist using:

ahdl_include "/path/to/the/veriloga_file.va"

4. SpectreHDL

An earlier propriatary behavioural modelling language. It's quite similar to
Verilog-A, and it is included using the ahdl_include command. It's use is
discouraged now, as all the effort is on Verilog-A instead.

5. SpectreMDL

The Measurement Description Language. This is a language for describing
re-usable measurements. It has not yet been fully implemented, but allows you
to do things similar (and more advanced) to the .measure commands found in
some other spice simulators. The language is spectre-like, but is normally
in a separate control file, and simulations performed using the "spectremdl"
command.

The language is also used in the "assert" statement in spectre (see
"spectre -h assert" from IC5033 onwards) which allows (with the expr=mdlExpr
parameter) MDL expressions to be used to compute assertion conditions.

Regards,

Andrew.

On 12 Apr 2004 13:28:14 -0700, wjcndyd@yahoo.com (Eric Lau) wrote:

A little bit confused about Spectre syntax. Besides the so-called
Spectre syntax, is MDL part of it? What about the syntax used in
Spectre format model card???
Please clarify. Thanks a million!
Eric

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd