How many dedicated clock pins EP20K1500EBC652 device?

[enq_semi]

How many dedicated clock pins are there for EP20K1500EBC652 device?

I only found clk1p,clk2p,clk3p,clk4p (Pin w34, u2, y34, t2) are
dedicated clock pins. However, clk1p and clk2p are connected together,
clk3p and clk4p are connected together; So I can only have two
different clock signals drive the internal clock trees.

According to APEX 20K Programmable Logic Device Family Data Sheet,
there are "up to eight global clock signals" in the APEX 20K device.
How many are there for EP20K1500 device and how can I have more than
two different external clocks to drive the different internal clock
trees?

thanks,

Yi Zhang
ENQ Semi

 

[Vaughn Betz]

enq_semi@yahoo.com (enq_semi) wrote in message news:<cd4a30b8.0311240726.3d82ce54@posting.google.com>...

How many dedicated clock pins are there for EP20K1500EBC652 device?

I only found clk1p,clk2p,clk3p,clk4p (Pin w34, u2, y34, t2) are
dedicated clock pins. However, clk1p and clk2p are connected together,
clk3p and clk4p are connected together; So I can only have two
different clock signals drive the internal clock trees.

According to APEX 20K Programmable Logic Device Family Data Sheet,
there are "up to eight global clock signals" in the APEX 20K device.
How many are there for EP20K1500 device and how can I have more than
two different external clocks to drive the different internal clock
trees?

thanks,

Yi Zhang
ENQ Semi

Hi Yi,

The APEX 20K has 8 dedicated, high speed global resources.
4 are dedicated clocks -- they are normally used only to route clocks.
Another 4 are "dedicated fast resources" or "fast clocks." They are
used to route either clocks or other high-fanout signals, like
asynchronous clears.

The two resources aren't much different. The dedicated clocks are
driven by dedicated input pins, while the fast dedicated networks can
be driven by bidirectional IOs or internal signals from the FPGA
fabric. So most people just consider this 8 dedicated clocking /
asynchronous clear networks.

clk1p and clk2p aren't connected together, so you can send 4 signals
in through the dedicated clock pins.

The FAST pins drive the dedicated FAST networks, which can be used as
another 4 clock networks:

network Driving pin
FAST1 B19
FAST2 B17
FAST3 AP19
FAST4 AP17

Hope this helps.

Vaughn
Altera

 

[enq_semi]

Vaughn,

Thank you very much for your help!

I was confused when reading apex.pdf: somewhere says 8 "dedicated
clock and input pins", somewhere says 4 "dedicated clocks". Now I know
the difference is that 4 "fast input pins".

One question: to access the "dedicated fast resources", do I simply
define an internal net as "global signal"? During compilation, I saw
msgs like "promote signal XXX to global signal automatically". Does it
mean it uses dedicated fast resources for that signal already?

The two resources aren't much different. The dedicated clocks are
driven by dedicated input pins, while the fast dedicated networks can
be driven by bidirectional IOs or internal signals from the FPGA
fabric. So most people just consider this 8 dedicated clocking /
asynchronous clear networks.

I just did an experiment: use pin Y34 (dedicated clock pin) to drive a
few small modules and I see clock skew of less than 0.1 ns; then I use
pin B19 (fast1) to drive the same modules, this time I see clock skew
of more than 1.1 ns; (skew observed from layout/floorplan view)

Do you think this skew will be too large for the hold-time of the
flip-flops on fpga?

clk1p and clk2p aren't connected together, so you can send 4 signals
in through the dedicated clock pins.

I wasn't clear in my first post: the FPGA is sitting on a DSP board,
so the clk1p and clk2p are connected. I probably will cut them apart.

The FAST pins drive the dedicated FAST networks, which can be used as
another 4 clock networks:

Same concern as I mentioned above: is > 1.1ns skew too large for them
to be used as clock networks?

thanks!

Yi

 

[Vaughn Betz]

Hi Yi,

My answers below.

Vaughn,

Thank you very much for your help!

I was confused when reading apex.pdf: somewhere says 8 "dedicated
clock and input pins", somewhere says 4 "dedicated clocks". Now I know
the difference is that 4 "fast input pins".

One question: to access the "dedicated fast resources", do I simply
define an internal net as "global signal"? During compilation, I saw
msgs like "promote signal XXX to global signal automatically". Does it
mean it uses dedicated fast resources for that signal already?

Yes, if you make an assignment to a net of "Global Signal = On" you
will force it to use a dedicated global clock or fast global clock
network. If you don't do this, Quartus will decide which signals get
the global networks. Generally relying on the automatic global
promotion code is fine -- it basically puts the highest fanout clocks
on global networks first, followed by lower fanout clocks, followed by
asynchronous clears, until it runs out of either clock/aclr signals or
global networks.

The two resources aren't much different. The dedicated clocks are
driven by dedicated input pins, while the fast dedicated networks can
be driven by bidirectional IOs or internal signals from the FPGA
fabric. So most people just consider this 8 dedicated clocking /
asynchronous clear networks.

I just did an experiment: use pin Y34 (dedicated clock pin) to drive a
few small modules and I see clock skew of less than 0.1 ns; then I use
pin B19 (fast1) to drive the same modules, this time I see clock skew
of more than 1.1 ns; (skew observed from layout/floorplan view)

Do you think this skew will be too large for the hold-time of the
flip-flops on fpga?

The skew you're seeing on pin B19 sounds way too large. Pin B19 can
drive both the fast network and regular routing. To make sure it uses
the fast network, make a "global signal = on" assignment to the output
signal of that pin. It sounds like you're just using regular routing
right now. If the signal you put on B19 is not a clock or
asynchronous clear, Quartus will tend to prefer to use regular
routing, rather than the Fast network, unless you make this setting.

Since pin Y34 can *only* drive the dedicated clock network, just
putting a signal there is enough to force usage of that network.

clk1p and clk2p aren't connected together, so you can send 4 signals
in through the dedicated clock pins.

I wasn't clear in my first post: the FPGA is sitting on a DSP board,
so the clk1p and clk2p are connected. I probably will cut them apart.


The FAST pins drive the dedicated FAST networks, which can be used as
another 4 clock networks:

Same concern as I mentioned above: is > 1.1ns skew too large for them
to be used as clock networks?

Their skew should be much better than that. Try the experiment above
to make sure you are really using the Fast networks.

Regards,

Vaughn
Altera

 

[enq_semi]

Hi, Vaughn,

Their skew should be much better than that. Try the experiment above
to make sure you are really using the Fast networks.

I made sure it should use the Fast networks:

1. In assignment manager I have the following settings:
-- aclk_in => Clock Settings = my_clk @ 56MHz
-- aclk_in => Global Signal = Global Clock
-- aclk_in => Auto Global Clock = On

2. During compile, I saw this message:
--Info: Promoted cell aclk_in to global signal automatically

I doubted that the timing parameters used by Quartus might not be
accurate, however, I verified two skews on oscilloscope against the
timing report by Quartus, the difference is very small (around 0.2 ns
or so).

I also tried non-clock and non-fast I/O pin, the skew is much larger.
So, maybe the 1ns skew with fast I/O pin is considered "useable as
clock"? (I certainly NOT hope so.)

Thank you very much for your help!

Yi

 

[Vaughn Betz]

enq_semi@yahoo.com (enq_semi) wrote in message news:<cd4a30b8.0311260745.35013640@posting.google.com>...

Hi, Vaughn,


Their skew should be much better than that. Try the experiment above
to make sure you are really using the Fast networks.


I made sure it should use the Fast networks:

1. In assignment manager I have the following settings:
-- aclk_in => Clock Settings = my_clk @ 56MHz
-- aclk_in => Global Signal = Global Clock
-- aclk_in => Auto Global Clock = On

Should really use
aclk_in => Global Signal = On

for APEX.

Global clock etc. are really for Stratix where there are multiple
types of globals; from the message below, it looks like they do not
get interpreted as "Global signal = on" for APEX.

2. During compile, I saw this message:
--Info: Promoted cell aclk_in to global signal automatically

Yup, looks like Quartus automatically promoted it to use global
routing. If it had recognized your global signal assignment, this
should have been done by your constraints though, and wouldn't require
the automatic global processing. Just FYI; the end effect is fine.

I doubted that the timing parameters used by Quartus might not be
accurate, however, I verified two skews on oscilloscope against the
timing report by Quartus, the difference is very small (around 0.2 ns
or so).

I also tried non-clock and non-fast I/O pin, the skew is much larger.
So, maybe the 1ns skew with fast I/O pin is considered "useable as
clock"? (I certainly NOT hope so.)

Hmmm ... I guess the 1 ns skew is correct then. The Fast networks in
APEX do have higher skew than the dedicated clock networks, so they do
hurt performance a bit. They still certainly do work as clocks with
no hold violations, since many designs use them that way -- the 1 ns
skew must be between cells that are separated by enough distance that
they have to use enough routing that the data delay is comfortably
above the clock skew.

Vaughn