C
c4cheema
Guest
Hi
Is this syntax is ok to keep a bit open in Xilinx EDK design
Net fpga_0_xyz<0> OPEN;
In my design I do not want to use few bit
and I do not want to edit hdl part.
Tell how do I remain it unused at top level
---------------------------------------
Posted through http://www.FPGARelated.com
Is this syntax is ok to keep a bit open in Xilinx EDK design
Net fpga_0_xyz<0> OPEN;
In my design I do not want to use few bit
and I do not want to edit hdl part.
Tell how do I remain it unused at top level
---------------------------------------
Posted through http://www.FPGARelated.com