How is it possible to design a convolutional interleaver wit

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In my interleaver design for FPGA, I am using an external SDRAM for data
storage.

The clock cycles required to write a frame into the RAM and read a frame
back to error correction unit ain't enough.

The interleaver has 40 rows, which contain 200 * 0, 1, ...39 pieces of data.
And one row of the RAM contains 256 data. The write/read pointers are
increased by 200*i or decreased by 200*i (0<i<39) for each write/read
operation.

As a result, nearly everytime I write one data or read one data, I have to
go
through a "open a new row, write or read 1 data, close the row" cycle. To
open
a row and close it, the memory requires some 10 clock cycles.

How is it possible to design it in such a way that memory write is in
sequential
order? That is, when a new frame arrives, I write into the RAM column by
until current row is filled, then open the next row.

I may have to read in a random access, but I can save a lot of clock cycles
in
the memory write.

FYI, my resources is some RTL logic and an SDRAM. The design can be made
with the FPGA's LUTs, but i don't own the resource.
 
On Mar 28, 3:36 pm, "news reader" <newsrea...@google.com> wrote:
In my interleaver design for FPGA, I am using an external SDRAM for data
storage.

The clock cycles required to write a frame into the RAM and read a frame
back to error correction unit ain't enough.

The interleaver has 40 rows, which contain 200 * 0, 1, ...39 pieces of data.
And one row of the RAM contains 256 data. The write/read pointers are
increased by 200*i or decreased by 200*i (0<i<39) for each write/read
operation.

As a result, nearly everytime I write one data or read one data, I have to
go
through a "open a new row, write or read 1 data, close the row" cycle. To
open
a row and close it, the memory requires some 10 clock cycles.

How is it possible to design it in such a way that memory write is in
sequential
order? That is, when a new frame arrives, I write into the RAM column by
until current row is filled, then open the next row.

I may have to read in a random access, but I can save a lot of clock cycles
in
the memory write.

FYI, my resources is some RTL logic and an SDRAM. The design can be made
with the FPGA's LUTs, but i don't own the resource.
Click to expand...

If you write out by hand the order in which data comes out of a depth-
N interleaver, you should be able to spot the pattern (it's really not
a very complicated pattern...).

You can then just apply this pattern to the read pointer, letting you
store your data in the original (sequential) order. In other words,
the interleaving is done during the read operation.

However, the read access pattern will be just as "random" as the write
access pattern was in your original design. So unless your SDRAM's
read cycle is shorter than its write cycle, this won't save you any
time.


--
Oli
 
On Mar 28, 11:21 am, "Oli Charlesworth" <c...@olifilth.co.uk> wrote:
On Mar 28, 3:36 pm, "news reader" <newsrea...@google.com> wrote:



In my interleaver design for FPGA, I am using an external SDRAM for data
storage.

The clock cycles required to write a frame into the RAM and read a frame
back to error correction unit ain't enough.

The interleaver has 40 rows, which contain 200 * 0, 1, ...39 pieces of data.
And one row of the RAM contains 256 data. The write/read pointers are
increased by 200*i or decreased by 200*i (0<i<39) for each write/read
operation.

As a result, nearly everytime I write one data or read one data, I have to
go
through a "open a new row, write or read 1 data, close the row" cycle. To
open
a row and close it, the memory requires some 10 clock cycles.

How is it possible to design it in such a way that memory write is in
sequential
order? That is, when a new frame arrives, I write into the RAM column by
until current row is filled, then open the next row.

I may have to read in a random access, but I can save a lot of clock cycles
in
the memory write.

FYI, my resources is some RTL logic and an SDRAM. The design can be made
with the FPGA's LUTs, but i don't own the resource.

If you write out by hand the order in which data comes out of a depth-
N interleaver, you should be able to spot the pattern (it's really not
a very complicated pattern...).

You can then just apply this pattern to the read pointer, letting you
store your data in the original (sequential) order. In other words,
the interleaving is done during the read operation.

However, the read access pattern will be just as "random" as the write
access pattern was in your original design. So unless your SDRAM's
read cycle is shorter than its write cycle, this won't save you any
time.

--
Oli
Click to expand...

I'm not sure how much it would help in your application unless your
interleave factor is constant, but using the 4 banks of the SDRAM is
generally a faster way to deal with high-speed data than attempting to
locate all data in a single row. SDRAM was designed such that the
row activate and precharge can be "buried" behind other operations
when multiple banks are used. So in essence if you can order your
storage such that each new data comes from a different bank in the
SDRAM you can cut your cycle time down significantly. Using the
minimum burst size (assuming you don't need more than one word
of data at a time) and read with autoprecharge (to avoid the
additional
command to "close" the row) you can get down to 2 cycles per read if
you rotate through all four banks. A control sequence for a regular
rotation through 4 banks might look like:
--- Startup section with some wasted cycles ---
Activate Row in Bank 0
NOP
Activate Row in Bank 1
NOP
Activate Row in Bank 2
--- Continuous high-bandwidth section
Read Col in Bank 0 with autoprecharge
Activate Row in Bank 3
Read Col in Bank 1 with autoprecharge
Activate Row in Bank 0
Read Col in Bank 2 with autoprecharge
Activate Row in Bank 1
Read Col in Bank 3 with autoprecharge
Activate Row in Bank 2
Read Col in Bank 0 with autoprecharge
Activate Row in Bank 3
Read Col in Bank 1 with autoprecharge
Activate Row in Bank 0
Read Col in Bank 2 with autoprecharge
Activate Row in Bank 1
Read Col in Bank 3 with autoprecharge
Activate Row in Bank 2
Read Col in Bank 0 with autoprecharge
Activate Row in Bank 3
Read Col in Bank 1 with autoprecharge
--- Closing section with some wasted cycles
NOP
Read Col in Bank 2 with autoprecharge
NOP
Read Col in Bank 3 with autoprecharge

Note that the mid-section can be repeated ad-naseum allowing
unlimited access length at this bandwidth. Also note that
each access includes its own Row and Column so other than
the bank restriction the order can be truly random.

HTH,
Gabor
 
Pipelining the four banks am I right? I will study this since this is the
first time I handle SDRAM.

Thank you for the pointer.




"Gabor" <gabor@alacron.com> wrote in message
news:1175116871.777082.190590@p15g2000hsd.googlegroups.com...
On Mar 28, 11:21 am, "Oli Charlesworth" <c...@olifilth.co.uk> wrote:
On Mar 28, 3:36 pm, "news reader" <newsrea...@google.com> wrote:



In my interleaver design for FPGA, I am using an external SDRAM for
data
storage.

The clock cycles required to write a frame into the RAM and read a
frame
back to error correction unit ain't enough.

The interleaver has 40 rows, which contain 200 * 0, 1, ...39 pieces of
data.
And one row of the RAM contains 256 data. The write/read pointers are
increased by 200*i or decreased by 200*i (0<i<39) for each write/read
operation.

As a result, nearly everytime I write one data or read one data, I have
to
go
through a "open a new row, write or read 1 data, close the row" cycle.
To
open
a row and close it, the memory requires some 10 clock cycles.

How is it possible to design it in such a way that memory write is in
sequential
order? That is, when a new frame arrives, I write into the RAM column
by
until current row is filled, then open the next row.

I may have to read in a random access, but I can save a lot of clock
cycles
in
the memory write.

FYI, my resources is some RTL logic and an SDRAM. The design can be
made
with the FPGA's LUTs, but i don't own the resource.

If you write out by hand the order in which data comes out of a depth-
N interleaver, you should be able to spot the pattern (it's really not
a very complicated pattern...).

You can then just apply this pattern to the read pointer, letting you
store your data in the original (sequential) order. In other words,
the interleaving is done during the read operation.

However, the read access pattern will be just as "random" as the write
access pattern was in your original design. So unless your SDRAM's
read cycle is shorter than its write cycle, this won't save you any
time.

--
Oli


I'm not sure how much it would help in your application unless your
interleave factor is constant, but using the 4 banks of the SDRAM is
generally a faster way to deal with high-speed data than attempting to
locate all data in a single row. SDRAM was designed such that the
row activate and precharge can be "buried" behind other operations
when multiple banks are used. So in essence if you can order your
storage such that each new data comes from a different bank in the
SDRAM you can cut your cycle time down significantly. Using the
minimum burst size (assuming you don't need more than one word
of data at a time) and read with autoprecharge (to avoid the
additional
command to "close" the row) you can get down to 2 cycles per read if
you rotate through all four banks. A control sequence for a regular
rotation through 4 banks might look like:
--- Startup section with some wasted cycles ---
Activate Row in Bank 0
NOP
Activate Row in Bank 1
NOP
Activate Row in Bank 2
--- Continuous high-bandwidth section
Read Col in Bank 0 with autoprecharge
Activate Row in Bank 3
Read Col in Bank 1 with autoprecharge
Activate Row in Bank 0
Read Col in Bank 2 with autoprecharge
Activate Row in Bank 1
Read Col in Bank 3 with autoprecharge
Activate Row in Bank 2
Read Col in Bank 0 with autoprecharge
Activate Row in Bank 3
Read Col in Bank 1 with autoprecharge
Activate Row in Bank 0
Read Col in Bank 2 with autoprecharge
Activate Row in Bank 1
Read Col in Bank 3 with autoprecharge
Activate Row in Bank 2
Read Col in Bank 0 with autoprecharge
Activate Row in Bank 3
Read Col in Bank 1 with autoprecharge
--- Closing section with some wasted cycles
NOP
Read Col in Bank 2 with autoprecharge
NOP
Read Col in Bank 3 with autoprecharge

Note that the mid-section can be repeated ad-naseum allowing
unlimited access length at this bandwidth. Also note that
each access includes its own Row and Column so other than
the bank restriction the order can be truly random.

HTH,
Gabor
Click to expand...
 
"Oli Charlesworth" <catch@olifilth.co.uk> wrote in message
news:1175095276.957406.238840@r56g2000hsd.googlegroups.com...
On Mar 28, 3:36 pm, "news reader" <newsrea...@google.com> wrote:
In my interleaver design for FPGA, I am using an external SDRAM for data
storage.

The clock cycles required to write a frame into the RAM and read a frame
back to error correction unit ain't enough.

The interleaver has 40 rows, which contain 200 * 0, 1, ...39 pieces of
data.
And one row of the RAM contains 256 data. The write/read pointers are
increased by 200*i or decreased by 200*i (0<i<39) for each write/read
operation.

As a result, nearly everytime I write one data or read one data, I have
to
go
through a "open a new row, write or read 1 data, close the row" cycle. To
open
a row and close it, the memory requires some 10 clock cycles.

How is it possible to design it in such a way that memory write is in
sequential
order? That is, when a new frame arrives, I write into the RAM column by
until current row is filled, then open the next row.

I may have to read in a random access, but I can save a lot of clock
cycles
in
the memory write.

FYI, my resources is some RTL logic and an SDRAM. The design can be made
with the FPGA's LUTs, but i don't own the resource.


If you write out by hand the order in which data comes out of a depth-
N interleaver, you should be able to spot the pattern (it's really not
a very complicated pattern...).

You can then just apply this pattern to the read pointer, letting you
store your data in the original (sequential) order. In other words,
the interleaving is done during the read operation.

However, the read access pattern will be just as "random" as the write
access pattern was in your original design. So unless your SDRAM's
read cycle is shorter than its write cycle, this won't save you any
time.


--
Oli
Click to expand...
Yeah, this is what I am looking for. For this algorithm, my question is,
what is the condition when
I am able to write from memory address 0 again when the first iteration is
over, without overwritting
the data already in the memory.

I was aware that, the read operations are with random addresses, however
writes are sequential.
If the write pointer flips back from upper bound to address zero too early,
it may overwrite some
data. How do I calculate the upper bound?
 
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