HOW IS GREY BOX VERIFICATION DONE

[Abbs]

hiii friends...

can any one tell me or explain to how is grey box verification done???
black box and white box is clear but how do we carry on with grey box,
what knowledge is known. can we do the same in only in testbench. we
check the output response the way done in black box, but as per
definition grey box has little knowledge about the design
implementation.

Thanks

Cheers.

Abbs

 

<..can we do the same in only in testbench. we
check the output response the way done in black box, but as per
definition grey box has little knowledge about the design
implementation.>
In his book "Writing testbenches" by Bergeron, he defines "a white-box
approach has full visibiliy and controlability of the internal
structure and implementation of the DUT".
"Grey-box verification is compromise between the aloofness of a
black-box verification and the dependence on the implementation of
white-box. A Grey-box approach controls and observes a design entirely
thru its top-level interfaces."

From these defintions, the white-box sees everything and can control
(e.g., force) everything. However, grey-box is like black, but knows

about the internal implementation. Control and observability is
limited to the interfaces, like the black-box.

For verification of any color, I like to use SystemVerilog Assertions
or PSL, possibly supported by auxiliary code. For example, assume that
the interface has "req" "ack" signals, and the internal has "ready",
bus_enable". In SVA, I can write:
// if req then an ack within 1 to 4 cycles -- black-box
ap_reqack: assert property (@ (posedge clk)
req |-> ##[1:4] ack);
// if req, then in 3 cycles ack -- grey-box (It knows of the
implementation)
// Note that spec states that ack can come in 1 to 4, but that one
specific
// implementation provides the ack in 3 cycles. Another
implementation may do
// it in 2 cycles, and that is OK, but the 2 cycle implementation will
fail the grey-box
// verification written for 3 cycles.
ap_req_ready_ack: assert property (@ (posedge clk)
req |-> ## 3ack);

--------------------------------------------------------------------------
Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
http://www.abv-sva.org/ ben@abv-sva.org
* Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
* Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115
---------------------------------------------------------------------------

 

The following is in error:
<However, grey-box is like black, but knows about the internal
implementation. >
That was left out in error and should have been deleted.
Sorry.
Ben