how instantiate generic vhdl entity with verilog ?

[kagior]

I've a problem with the unisim_VITAL library : inside there is a
generic component (LUT3) and i want to initialize it with a verilog
module:

LUT3 mymodule(I0,...); defparam mymodule.INIT=8'hB4;

I'm using NCSIM for the elaboration and i've the following error :

ncelab: *E,CFIGNV (/verilog_module.v,9862|47): VHDL generic LUT3.INIT
(/unisim/src/unisim_VITAL.vhd: line 26656, position 7) must have a
default value

Did anyone know how to cope with this problem ?

Thanks

 

[Ajeetha]

Hi,
Try parameter over-riding during instantiation, i.e.

instead of:

LUT3 mymodule(I0,...); defparam mymodule.INIT=8'hB4;

Try:

LUT3 #(8'hB4) mymodule(I0,...);

Regards
Ajeetha
http://www.noveldv.com

 

I would guess that it might work better if you used a parameter
override on the instantiation rather than a defparam. That would map
into setting a generic value the way VHDL does it. The Verilog
constructs of defparams and hierarchical names are rather alien to
VHDL, and may not work across language boundaries.

In other words, try

LUT3 #(8'hB4) mymodule (IO,...);

or

LUT3 #(.INIT(8'hB4)) mymodule (IO,...);

 

[kagior]

Thanks for you help but none of yours solutions worked. I
re-synthetise the entity and extract the vhdl description, and now it
works. Maybe the problem comes from cadence...i don't know.

thank you

sharp@cadence.com wrote in message news:<1114101122.856802.179690@z14g2000cwz.googlegroups.com>...

I would guess that it might work better if you used a parameter
override on the instantiation rather than a defparam. That would map
into setting a generic value the way VHDL does it. The Verilog
constructs of defparams and hierarchical names are rather alien to
VHDL, and may not work across language boundaries.

In other words, try

LUT3 #(8'hB4) mymodule (IO,...);

or

LUT3 #(.INIT(8'hB4)) mymodule (IO,...);