How in VHDL do I write formatted spreadsheet file of my sign

[G Iveco]

After reading textbook for a while, I can't figure out how to write
formatted
texts. It seems this language is so complicated but fails to address the
simplest
tasks.

How do I convert signed into bit vectors?

 

[Jonathan Bromley]

On Sun, 22 Jul 2007 22:41:24 +0800,
"G Iveco" <G.Iveco@google.com> wrote:

After reading textbook for a while, I can't figure
out how to write formatted texts.

The (genuinely standard) package STD.TEXTIO provides basic
file I/O functionality; the (non-standard, but universally
available) package IEEE.STD_LOGIC_TEXTIO extends TEXTIO
to permit reading and writing of text representations
of STD_LOGIC_VECTOR and its friends.

It seems this language is so complicated but
fails to address the simplest tasks.

It seems that you're trying to translate Verilog line-for-line
into VHDL. One language does some things well, the other does
different things well. Some creative rearrangements will pay
handsome dividends, but naive translation is a sure road to
frustration. The lack of unconstrained subprogram arguments
and return types in Verilog is a massive source of frustration
to me when translating VHDL to Verilog. Your earlier question
about probing hierarchically-named objects is by far the
biggest problem when translating Verilog testbench code to VHDL.
File I/O is not a problem, but there is some drudgery in it.

How do I convert signed into bit vectors?

Why do you want to? If you need to do this because you
can read and write bit_vector using STD.TEXTIO, then I
suggest that you instead consider using STD_LOGIC_TEXTIO.

library ieee;
use std.textio.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
---
entity just_for_example is end;
architecture A of just_for_example is
begin
process
constant SLV: std_logic_vector(7 downto 0) := X"A5";
constant NUM: signed(7 downto 0) := to_signed(42, 8);
file F: text;
variable L: line;
begin
file_open(F, "stuff.txt", write_mode);
write(L, SLV); --- writes binary representation "10100101"
write(L, string' (", "));
hwrite(L, SLV); --- writes hex representation "A5"
write(L, string' (", "));
write(L, to_integer(NUM)); --- writes ordinary number "42"
write(L, string' (", "));
hwrite(L, std_logic_vector(NUM)); --- writes hex form "2A"
writeline(F, L); --- spit it out to the file
file_close(F);
wait;
end process;
end;

I agree that the syntax for text output is a tad clunky - that
has its roots in VHDL's insistence that it should be independent
of all the various operating systems that were around at the time
it was created. But it is *very* easy to sugar that syntax by
creating a few procedures to perform your own special-purpose
file I/O operations (such as dumping a bunch of signals out to
a comma-separated line of text). There are a few packages around
that use such tricks to mimic C "printf" or similar formatted I/O;
see, for example, Ben Cohen's website
http://members.aol.com/vhdlcohen/vhdl/Models.html

or the freebies section of EASICS:
http://www.easics.com/webtools/freesics

To answer directly your complaint about "how do I convert":
WHENEVER you need a type conversion, and you can't find
what you want in the standard packages, WRITE A FUNCTION.
Then you have the feature you need, ready for immediate use.

function to_bitvector(s: signed) return bit_vector is
begin
assert not is_X(std_logic_vector(s))
report "Converting SIGNED with unknown bits - using '0'"
severity warning;
for i in s'range loop
bv(i) := to_bit(s(i));
end loop;
return bv;
end;

The guts of this function could have been replaced by the
std_logic_1164 function "to_bitvector(s:std_ulogic_vector)"
as follows:

return to_bitvector(std_logic_vector(s));

but it's more instructive to see the for-loop formulation,
because you can use that in all kinds of situations where
there are no pre-defined conversions. is_X() and to_bit()
are predefined in std_logic_1164, but even if they weren't
you could very easily write your own.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Ralf Hildebrandt]

G Iveco schrieb:

After reading textbook for a while, I can't figure out how to write
formatted
texts. It seems this language is so complicated but fails to address the
simplest
tasks.

Verilog-XL was even worse ;-) If you use the C-like functions of Verilog
2000 you should have a look at the C-like text-I/O functions for VHDL:
<http://bear.ces.cwru.edu/vhdl/>.

Ralf