How in Design Compiler disable writing out "Assign" statemen

[Frank]

I was aware that there is a flag which can disenable Design Compiler to
write Assign statement. My NCVerilog gave me warning on Assign statement
when performing gate level simulations.

Many thanks in advance.

 

[Ajeetha]

Frank,
See:

http://www.deepchip.com/posts/0184.html

HTH
Ajeetha
www.noveldv.com