how i declare array for input port

K

kunal

Guest
hi
if i declare array for input port like input [1:0] in [7:0];
it is giving syntax error.
if i use reg then its ok but reg is use for input port.
my question is how to declare array for input port.
 
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kunal wrote:
hi
if i declare array for input port like input [1:0] in [7:0];
it is giving syntax error.
if i use reg then its ok but reg is use for input port.
my question is how to declare array for input port.
Click to expand...
You can't have an array for a port, input or output, in Verilog.

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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Stephen Williams wrote:

;

You can't have an array for a port, input or output, in Verilog.
Click to expand...
-> Transform the 2D-vector into a 1D-vector: input inp [15:0];
You map map it to a 2D-vector inside the module - if you really need it.

Ralf
 
input [15:0] in;

wire [1:0] in_A[0:7];
assign in_A[0] = in[1:0];
assign in_A[1] = in[3:2];
assign in_A[2] = in[5:4];
assign in_A[3] = in[7:6];
assign in_A[4] = in[9:8];
assign in_A[5] = in[11:10];
assign in_A[6] = in[13:12];
assign in_A[7] = in[15:14];

to access...
foo[1:0] <= in_A[4];
bar[1:0] <= in_A[1];
 
but the wire is not supported
i used like
module mux8_1 (in, sel, out);
input [1:0] in [7:0];// input is array of 8 bit of 2 bit width
input[2:0] sel;
output[1:0] out;
reg[1:0] out;

always @(in or sel)
begin
case (sel)
3'b000 : out = in[0];
3'b001 : out = in[1];
3'b010 : out = in[2];
3'b011 : out = in[3];
3'b100 : out = in[4];
3'b101 : out = in[5];
3'b110 : out = in[6];
default : out = in[7];
endcase
end
endmodule
how i declare aaray having width like above to work mux properly.
 
Certainly Ralf's wire technique is supported. Arrays are permitted for
wires or regs, but ARRAYS ARE NOT PERMITTED FOR INPUTS OR OUTPUTS IN
VERILOG as Steve already mentioned. Thus, arrays can only be used
*within* a module and you need to flatten the array into a single
dimensional vector for ports. Then wherever you instantiate the
module, you can map the input and outputs back into a array (reg or
wire) for ease of use in the instantiating (parent) module.

SystemVerilog supports array ports.



---
PDTi [ http://www.productive-eda.com ]
SpectaReg -- Spec-down code and doc generation for register maps


kunal wrote:
but the wire is not supported
i used like
module mux8_1 (in, sel, out);
input [1:0] in [7:0];// input is array of 8 bit of 2 bit width
input[2:0] sel;
output[1:0] out;
reg[1:0] out;

always @(in or sel)
begin
case (sel)
3'b000 : out = in[0];
3'b001 : out = in[1];
3'b010 : out = in[2];
3'b011 : out = in[3];
3'b100 : out = in[4];
3'b101 : out = in[5];
3'b110 : out = in[6];
default : out = in[7];
endcase
end
endmodule
how i declare aaray having width like above to work mux properly.
Click to expand...
 
I think a generate statement can also be used for situations where N
(the number of array elements) gets unmanageable (or is generic). This
would be the same as above but would only have one assign statement,
wrapped in a generate block, and the indexes would be a function of the
generate index.

---
PDTi [ http://www.productive-eda.com ]
SpectaReg -- Spec-down code and doc generation for register maps
 
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