J
James Harris
Guest
Warning, newbie question ahead. Give the following which I've put at
the top of a Verilog module
parameter BITS = 32;
I need a counter to count down from BITS to zero (inclusive) so the
counter needs to be something like floor(log2(BITS)) + 1 wide. For
example, if the parameter is 32 the counter needs to be 6 bits wide
and if the parameter is 8 the counter needs to be 4 bits wide. I tried
defining the width of the counter as
reg[log2(BITS) + 1] counter;
but this fails. There seems to be no way to take log2 - or any other
type of log - at compile time. I've ended up with
parameter LOG2BITS = 4;
parameter BITS = 2 ** LOG2BITS;
...
reg[LOG2BITS + 1] counter;
where LOG2BITS is set first then BITS is set based on the value of
LOG2BITS.
Is there a better way of doing this?
James
the top of a Verilog module
parameter BITS = 32;
I need a counter to count down from BITS to zero (inclusive) so the
counter needs to be something like floor(log2(BITS)) + 1 wide. For
example, if the parameter is 32 the counter needs to be 6 bits wide
and if the parameter is 8 the counter needs to be 4 bits wide. I tried
defining the width of the counter as
reg[log2(BITS) + 1] counter;
but this fails. There seems to be no way to take log2 - or any other
type of log - at compile time. I've ended up with
parameter LOG2BITS = 4;
parameter BITS = 2 ** LOG2BITS;
...
reg[LOG2BITS + 1] counter;
where LOG2BITS is set first then BITS is set based on the value of
LOG2BITS.
Is there a better way of doing this?
James