How does PLL with frequency translation work?

[Sommes]

I'm not very understand how does the divide by n counter work?
Thank you

 

[Rich.Andrews]

"Sommes" <j@jl.com> wrote in news:clphvf$q4f$1@news-02.connect.com.au:

I'm not very understand how does the divide by n counter work?
Thank you

A lot of PFM with a little bit of smoke and very tiny mirrors. &gt

For me to properly explain a PLL that uses a frequency divider would require
at least a pen and paper. Do you have one that you are working on that might
be used as an example?


r

--
Nothing beats the bandwidth of a station wagon filled with DLT tapes.

 

[Rene Tschaggelar]

Sommes wrote:

I'm not very understand how does the divide by n counter work?

It outputs a pluse every n pulses. It does so by a state maching
having usually 2^m states, which is equal or somewhat above n.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

 

[Tam/WB2TT]

"Sommes" <j@jl.com> wrote in message
news:clphvf$q4f$1@news-02.connect.com.au...

I'm not very understand how does the divide by n counter work?
Thank you


Take a simple example. Say you have a decade counter, like a 74x160, which

divides by 10, and you want to program it to divide by 6. Preload the
counter with 10-6=4. Now the counter goes 4,5,6,7,8,9. On a count of 9 a
carry is generated, which loads a 4 into the counter on the next clock
cycle, and it keeps going on like that foreever.

Anothe kind of counter is a down counter. A decade down counter counts
9,8,7,6,5,4,3,2,1,0. To figure out the load for these is easy. To divide by
6, you just load a 6, and the counter goes 6,5,4,3,2,1,0/6. Here you load
the 6 during the SAME clock cycle during which it reached 0.

Tam