How does ISE6 handle mixed-edge design?

[Tungsten-W]

Hi, group:

I use only rising edge and global buffers, but this oddball handed me a
module with a mixed clock design,
it uses both rising & falling edge of same clock. How come the P&Red netlist
and RTL simulation didn't
match. It seems the falling edge register has been removed.

The registers can be found in the netlist, but in gatelevel simulation, the
data is fed through with a small
wire delay only.

Is this the right behavior of mixed edge designs?

Best Regards,
Kelvin

 

[Tungsten-W]

Got it. It was testbench problem. His mixed edge module is working fine.



Tungsten-W <kelvin8157@hotmail.com> wrote in message
news:40357855@news.starhub.net.sg...

Hi, group:

I use only rising edge and global buffers, but this oddball handed me a
module with a mixed clock design,
it uses both rising & falling edge of same clock. How come the P&Red
netlist
and RTL simulation didn't
match. It seems the falling edge register has been removed.

The registers can be found in the netlist, but in gatelevel simulation,
the
data is fed through with a small
wire delay only.

Is this the right behavior of mixed edge designs?

Best Regards,
Kelvin