How does always_ff ensure sequential logic

[parag_paul@hotmail.com]

It may be a very wide question to answer,
but somehow the new LRM is quiet about it. It only says that the
simulators can do additional check to see that the behavior is
confirming


It says the following "it contains only one event control " but the
example shows more than that.
I am confused. Is pasting the LRM allowed here or infringes the copy
rights somewhere?

 

[Jonathan Bromley]

On Fri, 24 Aug 2007 03:39:20 -0700,
<parag_paul@hotmail.com> wrote:

It may be a very wide question to answer,
but somehow the new LRM is quiet about it. It only says that the
simulators can do additional check to see that the behavior is
confirming

Yes, it's not as robust a definition as some of us would like.
Given that always_ff was specifically designed for synthesis,
it would perhaps have been useful to mandate some simulation-time
checks that the code is synthesisable. If I remember correctly,
though, always_ff requires that any variables written within it
should be written from nowhere else - a useful check.

By contrast, the language rules for always_comb really do provide
a useful set of checks that you have a synthesisable block of
combinational logic.

It says the following "it contains only one event control " but the
example shows more than that.

No, it doesn't. The example is something like

always_ff @(posedge clk or posedge reset)
if (reset)
...
else
...

Although the event control contains two "posedge" event expressions,
there's still only exactly one event control - the whole @(...) is
known as an "event control". The key point is that there should be
precisely one point in the procedural code where it can wait;
all the remaining code should be zero-time execution. It's not
absolutely essential for the event control to be at the start of
the code, but of course that's the usual place to put it, and
that's the way you make a standard synthesisable always block.

I am confused. Is pasting the LRM allowed here or infringes the copy
rights somewhere?

Too hard, legal question, don't know the answer!

From a practical point of view I don't see how you can
intelligently discuss an LRM without making brief quotes from it.
On the other hand, cut-and-paste of entire sections would probably
be pushing your luck.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[parag_paul@hotmail.com]

Thanks for the quick re ply. ( Do you ever sleep )
What is syntax for the mulitple event controls in an always block.

Also , how can @ event control describe flow in an intial block


initial begin

@(posedge clk )

#10 ...

Where the clk is 0,1,0,1 at 0,5,10,15...; NS
Am I correct by saying that, whenever the simulation engine sees an
@ ,it will wait for the event, Is it like wait @(posedge clk ) .

-Parag

 

[Jonathan Bromley]

On Fri, 24 Aug 2007 04:20:01 -0700,
<parag_paul@hotmail.com> wrote:

Do you ever sleep

Not normally during the daytime! But sometimes work
takes me to other timezones... I'm nicely on GMT+1 now.
This week.

What is syntax for the mulitple event controls in an always block.

That's quite a loaded question....

'initial' is a way to create procedural code in Verilog.
'always' is exactly equivalent to 'initial forever',
a procedural block that infinitely loops.

Any procedural statement can have a timing control
as a prefix:

#5 a = b+1;
@(posedge clk) q <= d;
wait (ready) flag = 1;
#5 begin
....
end

Each timing control (#, @, wait) simply stalls execution
of the procedural flow until the timing control is
satisfied:

@() waits until an event occurs...
@(sig1 or sig2 or sig3)
waits for a change (event) on any of the signals
@event_name
waits until the event is triggered by ->event_name
@(posedge...)
waits until the specified transition

# waits for a time delay

wait() waits until its expression becomes nonzero (true),
but if the expression is already nonzero then it proceeds
without any delay (contrast the WAIT UNTIL statement in VHDL
which always waits even if its expression is already true).

Also , how can @ event control describe flow in an intial block

See above. You can put timing controls anywhere you like in
your procedural code. Of course, only some special forms
are synthesisable.

That's it. There's nothing subtler than that. The standard
form

always @(...) begin
...
end

*appears* to say "execute this code every time the event occurs",
but in fact it says
wait for the event to occur;
execute the code;
then loop back to the @() all over again.

Hope this helps.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Chris F Clark]

To extend what Jonathan said, you can even nest timing controls.

Thus:

@(posedge clock) #(5) a <= b;

waits for the positive edge of the clock to occur and then waits 5
(timesteps?, I can't recall the terminology used here) after that
before executing the non-blocking assignment.

#(5) @(posedge clock) a <= b;

waits the 5 timesteps first and then waits for the posedge.

@(negedge reset) @(posedge clock) a <= b;

waits on a reset negedge, and then waits on a clock posedge.

And you can (in behavioral (non-synthesizable) code) write all sorts
of timing constructs.

initial begin
q <= 0;
#(1) // get past time 0
@(posedge reset) // wait for reset to be de-asserted
forever @(posedge clock or negedge reset)
if (reset) q <= d;
else q <= 0;
end

 

[parag_paul@hotmail.com]

Does the wait in Verilog differ from always in the sense that, wait
will continue flow immediately if the expression is true now and
always will wait for the next time it is true !

 

[Jonathan Bromley]

On Sun, 26 Aug 2007 01:16:29 -0700,
<parag_paul@hotmail.com> wrote:

Does the wait in Verilog differ from always in the sense that, wait
will continue flow immediately if the expression is true now and
always will wait for the next time it is true !

Please be VERY CAREFUL....

'always' is NOT an event control or timing control.

'always' is a module-level statement that allows you to
create a static process (a block of simulation functionality)
described by a single procedural statement that executes
over and over again. For example,

reg a;
always a = (a===1'b0); // OUCH!!!

of course this is crazy code, because it repeatedly
toggles 'a' in zero time, then loops back and toggles 'a'
again, and so on.... so the simulator is permanently
busy at time 0, and simulation is stuck at time 0 and
simulated time can never move forward. So it is
fairly obvious that the code in the body of an "always"
statement must include some form of time delay or
wait-for-event. The most common way,
but NOT the only way, to do this is

always @(SOME_EVENT) ...

Please note that the event control @(SOME_EVENT) is NOT
part of the 'always'. It is part of the procedural code
that forms the body of the 'always'. Here are some other
possibilities...

always begin // No time delay here.
... // Do some zero-time procedural code.
#5 // Introduce a time delay.
... // Do some more code.
end // Loop back to the top of the "always".

always begin
... // Do some code.
@(posedge clk); // Wait until an active clock edge.
end // Loop back and start all over again.

So, let's go back to the common situation:

always @(posedge clock)
q <= d;

Everybody writes the code like that; consequently, lots of
people believe that 'always' is in some way associated with
the event control @(posedge clock), but they are WRONG!
This layout makes more sense....

always
@(posedge clock) q <= d;

Here we see clearly that @(posedge clock) is nothing more
than a PREFIX to the procedural statement q<=d; and it's
that whole procedural statement, complete with its prefix,
which forms the body of the 'always'.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

To answer the question that I *think* you asked:

There are three kinds of procedural delay in Verilog.
Any of these procedural delays can be used as a prefix
to any procedural statement. As Chris Clark pointed out,
you can also have more than one prefix on any procedural
statement. Of course, the rules for synthesis are much
more strict; they allow for only certain special uses
of @().

#(expression)
waits for the time delay specified by the value of (expression).

wait(expression)
waits until (expression) becomes non-zero. If (expression) is
already non-zero, wait() does NOT delay.

@(event_expression)
waits until (event_expression) happens. (event_expression) can
be built up from named events, posedge/negedge expressions, or
simply the value of an expression - if the expression changes
its value, the @() is released.

I *think* this is exactly what I said in an earlier post.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.